Applied Mechanics and Materials Vols. 385-386

Abstract: In order to solve the problem that existing underwater GPS positioning technology can only realize positioning underwater target installing acoustic transponder, the underwater target positioning system having good dependability with ultra-short baseline (USBL), forward looking sonar (FLS) and GPS receiver was designed. Using the system to position presetting underwater target in the offshore area of Dalian, positioning accuracy reached 1.2m, according with theoretical derivation, and verifying the feasibility using the system to obtain the latitude and longitude of underwater target in WGS-84 coordinate system.

Abstract: In order to obtain the key parameters which required by the Vehicle-Carrying test, the multi-channel data acquisition system based on CompactRIO embedded platform was developed. This system was satisfied the requirement of high reliability, inexpensive, portable and rapid configuration, Then, synchronized control technology such as queue, FIFO, interrupt and the superior system architecture which is compare to the state machine has been introduced in detail. Finally, availability and stability of the system were proved through the pressure text of data acquisition.

Abstract: In this paper, two ku band SSPAs using GaAs and GaN MMICs respectively were developed. Both of all have a same 8-way combining architecture and a same packaging module. The two SSPAs were measured on a same pulse width and duty cycle with different drain voltages. Compared with the GaAs SSPA, the GaN SSPA is more compact and efficient.

Abstract: The cause of generating glitch during the use of FPGA for designing electronic system is discussed. Signals have certain delay when passing through the FPGA device, thereby making the combinational logic output to generate sequencing, and some incorrect glitch signals could be generated, which affect the stability of the circuit. The article proposes that methods of gray code, delay method and synchronous circuit can be adopted to reduce glitch interference in FPGA design from the aspects of software and hardware, the above method is comprehensively used in designing electronic design to ensure that the system is not affected by glitch, thereby improving the reliability of the system.

Abstract: According to the requirements of the functional safety temperature transmitter high reliability, this paper selects the micro-power voltage reference, the reset monitor, the D-type flip-flop and the OR gate to design the functional safety temperature transmitter protection circuit for fault status. The protection circuit takes power from the data line of HART fieldbus by micro-power voltage references. According to the control signal of the functional safety transmitter, the protection circuit utilizes the state latch of D-type flip-flop, and realizes the functional safety temperature transmitter protection circuit for fault status.

Abstract: A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

Abstract: The scheme of FPGA hardware implementation based on the RA structure of encoder for q-ary LDPC codes as well as the Max-log-BP decoding are designed emphasisly. Form the performance, speed, and resource consumption situation of coder and decoder, this scheme based on FPGA can meet the requirements of the most of communication systems.

Abstract: This article introduces an efficient solar charging system based on FPGA. The charging circuit composed of BUCK-BOOST switch converter, realizes the function of maximum power point tracking (MPPT) of solar cells by using high speed controller---FPGA and a new MPPT technology---WVSVH P&O method. This paper explains the design and simulates it. The simulation results show the topology is able to achieve the purpose of charging efficiently.

Abstract: A planar power divider operating over the whole Ku-band is presented. The proposed device utilizes a T-microstrip junction combined with defected ground structure and an elliptical patch at the centre of the T-junction. An isolation resistor is connected across the slotted ground plane. The simulated results of the divider show equal power split, insertion loss is less than 0.3dB, return loss of all ports are better than 15dB, and isolation is better than 15dB over the whole Ku-band.

Abstract: This paper presents a design scheme of 5.1-channel wireless audio system which takes the advantages of Zigbee and PurePath Wireless technologies. It overcomes several disadvantages of traditional wired audio system such as inconvenience of speaker placement, complexity of wiring, low efficiency, etc. This system adopts a star topology structure with a host and six slave machines. System management is based on Zigbee network, and digital audio is transmitted via PurePath Wireless audio link. The CC8530 audio transceiver chips and IEEE 802.15.4 RF chips were adopted as the hardware platform and the Zigbee protocol stack was adopted as the core software. The results show that this method makes the wireless audio system low-cost, low-power and low-complexity. In addition, audio quality and system efficiency are both greatly enhanced.