Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

Abstract:

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

Info:

Periodical:

Edited by:

Yuanzhi Wang

Pages:

73-78

DOI:

10.4028/www.scientific.net/AMM.39.73

Citation:

J. T. Jiang et al., "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration", Applied Mechanics and Materials, Vol. 39, pp. 73-78, 2011

Online since:

November 2010

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$35.00

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