Drain Side N+ Layout Manners ("npnpn" Arranged-Type) on ESD Robustness in the 60-V pLDMOS-SCR

Shen Li Chen; Yu Ting Huang; Chih Hung Yang; Chih Ying Yen; Kuei Jyun Chen; Yi Cih Wu; Jia Ming Lin

doi:10.4028/www.scientific.net/AMM.870.401

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 870Drain Side N+ Layout Manners ("npnpn"...

Drain Side N⁺ Layout Manners ("npnpn" Arranged-Type) on ESD Robustness in the 60-V pLDMOS-SCR

Abstract:

Electrostatic-discharge (ESD) immunity measurements of different layout manners in the drain-side of HV pLDMOS devices are investigated in this paper. Here, eleven kinds of drain-side "npnpn" arranged-types of pLDMOS-SCR parasitic structure are used to evaluate the layout impacts on ESD robustness. In this study, at first the layout type of N⁺ region is continuous extended into the drain-side P⁺ cathode. Secondly, the layout type of N⁺ region is modulated by some discrete-distributed areas in the drain-side. From the experimental results, we can find that the ESD capability of the continuous extended and discrete distributed in the drain-side can be promoted, where all of the secondary breakdown current (I_t2) values can be achieved 7 A. However, the discrete-distributed layout type has higher breakdown voltage (V_BK) than that of the reference group (the pure none modulated pLDMOS-SCR npnpn-type structure). Therefore, the discrete-distributed layout types show good electrical properties and reliability immunities.

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Periodical:

Applied Mechanics and Materials (Volume 870)

Pages:

401-406

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.870.401

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Online since:

September 2017

Authors:

Shen Li Chen*, Yu Ting Huang, Chih Hung Yang, Chih Ying Yen, Kuei Jyun Chen, Yi Cih Wu, Jia Ming Lin

Keywords:

Electrostatic Discharge (ESD), Holding Voltage (V_h), p-Type Laterally-Diffused Metal-Oxide-Semiconductor (pLDMOS), Secondary Breakdown Current (I_t2), Trigger Voltage (V_t1)

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