Instability Effect on CLC nTFTs with Positive-Bias Temperature Stress

Abstract:

The positive-bias temperature instability (PBTI) test is one of effective reliability evaluation tests in negative-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) to expose the bonding interface between channel surface and gate dielectric and the integrity of gate dielectric. Adopting this test metrology in thin-film transistor (TFT) on glass substrate to reveal the previous concerns is still suitable. Using this good methodology in continuous-wave (CW) green laser-crystallization (CLC) poly-Si TFT, demonstrating a greatly effective mobility 530 cm^2/V-s, is necessary to interpret the defect generation and the device degradation under high gate-voltage stress and temperature impact, 25 oC to 125 oC. Because the channel surface of the CLC poly-Si TFT was not strictly smooth, the micro roughness in this stress caused more generation of interface states. The grain-boundary trap states in poly-crystalline channel, additionally, were generated after stress.

• Periodical: Advanced Materials Research (Volumes 314-316)
• Pages: 1918-1921
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.314-316.1918
• Online since: August 2011
• Authors: Mu Chun Wang, Hsin Chia Yang
• Keywords: CLC, Instability, Interface Trap States, Stress, Temperature, TFT

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