Design and Simulation of Low-Power Multistage Amplifiers
This paper presents a low-power multistage amplifier with a novel capacitor-multiplier frequency compensation (CMFC) technique. The proposed compensation strategy can allow the circuit to occupy less silicon area and to drive large capacitive loads more effectively. Moreover, smaller physical capacitance results in higher gain-bandwidth product (GBW) and improved transient responses. Furthermore, the capacitor multiplier stage (CMS) embedded in CMFC creates a left-half plane (LHP) zero, which boosts the phase margin and enhances the stability of the amplifier. Implemented in a commercial 0.5-μm CMOS technology and driving 500pF capacitive load, a three-stage CMFC amplifier achieves over 120dB gain, 1.699MHz GBW and 1.625V/μS average slew rate, while only dissipating 330μW under 3.3V supply.
Brendan Gan, Yu Gan and Y. Yu
M. Y. Ren "Design and Simulation of Low-Power Multistage Amplifiers", Advanced Materials Research, Vols. 378-379, pp. 655-658, 2012