Use N+ Buried Layer to Design a Low On-Resistance VDMOS

Abstract:

A novel structure of a VDMOS in reducing on-resistance is proposed and experimentally demonstrated with a 200V N-channel VDMOS. With this structure, the on-resistance value of the VDMOS is reduced by 19.6% than that of a traditional VDMOS structure as the breakdown voltage almost maintained the same value, and there is only one additional mask in processing this new structure VDMOS, which is easily fabricated. By TCAD tool, the specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in high-voltage VDMOS and BCD areas.

• Periodical: Advanced Materials Research (Volumes 756-759)
• Pages: 4267-4270
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.756-759.4267
• Online since: September 2013
• Authors: Zhao Huan Tang, Bin Wang, Jia Nan Wang, Kai Zhou Tan
• Keywords: Breakdown Voltage, N+ Buried Layer, On-Resistance, VDMOS

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