Defect and Diffusion Forum Vol. 452

Abstract: The fabrication of n-channel IGBTs is constrained by the low conductivity as well as poor quality of the p-type SiC substrate. This paper reports 6-inch high quality p-type 4H-SiC wafers achieved by PVT method. The wafers were examined by synchrotron X-ray topography indicating average defect densities are on par or better than commercial 6-inch n-type wafers. Large areas of the wafer, especially the middle region of the wafer is characterized by very low density of BPDs. The extent of prismatic slip due to radial thermal gradients is also vastly reduced compared to typical n-type wafers.

Abstract: The extensive study of point defects in 4H-SiC over the past two decades has led to a comprehensive understanding of their influence on device performance. Specifically, the dominant defects Z_1/2 and EH_6/7 have been well-quantified and are now formally assigned to specific states of the carbon vacancy. Building upon this foundational knowledge, our study investigates the defect landscape created by the novel process of Energy-Filtered Ion Implantation (EFII). Using DLTS and MCTS measurements conducted within the temperature range of 50−650 K, we analyzed the trap levels created by 19 MeV Nitrogen implantation in as-grown 4H-SiC epitaxial wafer. The majority carrier (electrons) trap with DLTS measurements reveal the presence of prominent peaks associated with carbon complexes, labeled as ON0a (E_c - 0.586 eV) and ON0b / Z_1/2 at (E_c - 0.681 eV), along with smaller peaks in the shallow region and a broader peak identified as EH_6/7 at (E_c - 1.53 eV) as the deepest peak. Notably, the close proximity of the ON0b peak to the well-known Z_1/2 peak poses a significant challenge, preventing the definitive assignment of a defect structure to the known carbon complexes. On the contrary, minority carrier (holes) trap detection with MCTS reveal B-center at (E_V + 0.24 eV) and (E_V + 0.33 eV) and a negligible shallow peak at (E_V + 0.22 eV) assigned as X center. There was no indication of D-center formation in the EFII implanted samples.

Abstract: Silicon carbide (SiC) is valued for high-power and high-frequency devices, but its performance is limited by crystalline defects. We report a newly observed defect arrangement, termed the “galaxy” defect, in wafers from a PVT-grown 6-inch 4° off-axis boule. Optical microscopy revealed dense clusters of micron-sized inclusions, while synchrotron X-ray topography (XRT) showed associated dislocation networks. Transmission synchrotron XRT indicated threading dislocation clusters, and grazing images revealed high densities of basal plane dislocations, deflected Frank partials, and threading-edge-dislocation low-angle grain boundaries (TED-LAGBs). The defect evolved as growth progressed, producing increasingly complex dislocation structures. Based on the observation, we proposed a mechanism for the evolution of the defect involving the generation, evolution, and interaction between the inclusions and dislocations.

Abstract: Silicon carbide is a leading wide-bandgap semiconductor for high-voltage power electronics. For 6.5–10 kV operation, thick epitaxial layers (≥60 µm) are required to sustain depletion width and maintain uniform electric fields, placing a premium on low extended-defect densities in both substrate and epilayer. Thick epitaxial 4H-SiC layers of 60 µm and 110 µm were grown on 6-inch substrates in a multi-wafer warm-wall reactor and evaluated by synchrotron X-ray topography in grazing-incidence (22-4 16) and transmission (11-20) geometries. Transmission imaging showed substrate dislocation content near the lower bound typically reported for 6-inch wafers. Notably, grazing-incidence topography (penetration depth >40 µm) revealed no basal-plane dislocations propagating into the epilayers, consistent with efficient dislocation conversion at the substrate–epilayer interface. The 3C-SiC inclusion density was ~30 per 6-inch wafer for 60 µm epilayers and ~60 per wafer for 110 µm epilayers; the average micropipes density varies from 0 to 5 for both 60 and 110 um epiwafers. Threading dislocation densities—screw, edge, and mixed—were on the order of 1.0–2.0 × 10³ cm⁻². These results establish thick 4H-SiC epilayers with suppressed basal-plane propagation and substantially reduced extended-defect content, providing a strong basis for reliable 6.5–10 kV device fabrication.

Abstract: The performance and reliability of silicon carbide (SiC) devices are critically dependent on the quality of epitaxial layers which in turn are influenced by substrate properties. The accurate classification of epitaxial defects coming from substrate crystal defects and surface defects is critical since these can adversely affect device performance. In this paper, two new methods of defect characterization in substrates and epitaxial layers are presented utilizing photoluminescence (PL) spectrum and carrier lifetime. These methods can be used to study the evolution of defects from substrates to epi and to better predict Epi yields.

Abstract: The fabrication of high-quality 4H-SiC epitaxial layers for power semiconductor devices involves complex processes including bulk crystal growth, wafer slicing, polishing, and chemical vapor deposition (CVD) epitaxy with precise step-flow control on slightly off-cut Si-face substrates. Despite advances, intrinsic crystallographic defects such as threading dislocations, basal plane dislocations, and stacking faults remain significant challenges, propagating into epitaxial layers and degrading device performance and reliability. This study examines defect types and their impact on 4H-SiC wafers, emphasizing the transition from 150 mm to 200 mm substrates, which introduces increased defect densities and polytype inclusions. Comprehensive defect characterization using advanced microscopy, molten KOH etching, and electrical wafer sorting reveals strong correlations between physical defects—such as micropipes, carrot-like stacking faults, and triangular 3C-SiC inclusions—and device failures, particularly under reliability stress tests like High Temperature Reverse Bias (HTRB). The findings highlight the critical role of substrate quality, epitaxial growth conditions, and defect mapping in improving yield and device robustness. This work underscores the necessity of integrating multi-scale defect inspection and targeted reliability assessments to optimize 4H-SiC power device manufacturing and performance.