The Device-Technological Simulation of Local 3D SOI-Structures

Igor T. Kogut; Victor I. Holota; Anatoly Druzhinin; V.V. Dovhij

doi:10.4028/www.scientific.net/JNanoR.39.228

Paper Titles

Electron Transport through Thin SiO₂ Films Containing Si Nanoclusters
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Hopping Conduction in Structures with Ge Nanoclusters Grown on Oxidized Si (001)
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Development and Modeling of Thermal Energy Harvesting Setup
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Selected Questions Related to Characterization of MEMS Structures Comprising PZT Piezo Layer
p.202

Morphology of the Interface “Silicon Wire - Nerve Fiber"
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Multichannel Fiber-Optic Ring Converters for Optical Sensors of Physical Quantities
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The Device-Technological Simulation of Local 3D SOI-Structures
p.228

Nanostructured Metal Films Formed onto Porous Silicon Template
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Precise Manipulations with Asymmetric Nano-Objects Viscoelastically Bound to a Surface
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HomeJournal of Nano ResearchJournal of Nano Research Vol. 39The Device-Technological Simulation of Local 3D...

The Device-Technological Simulation of Local 3D SOI-Structures

Abstract:

This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.

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Periodical:

Journal of Nano Research (Volume 39)

Pages:

228-234

DOI:

https://doi.org/10.4028/www.scientific.net/JNanoR.39.228

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Online since:

February 2016

Authors:

Igor T. Kogut, Victor I. Holota, Anatoly Druzhinin*, V.V. Dovhij

Keywords:

CMOS Transistor Array, Layout, Local 3D SOI Structure, Microcavities, Si Substrate

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* - Corresponding Author

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