Comparative Performance Analysis of Multi Gate Tunnel Field Effect Transistors

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In this paper, analytical modelling and performance analysis of novel device structures such as single gate SOI Tunnel Field Effect transistor (SG SOI TFET), Dual-Material Gate TFET (DMG TFET) and Dual Material Double Gate TFET (DMDG TFET) are proposed. The performance of the three devices is studied and compared in terms of surface potential, electric field and drain current. The DMDG TFET shows better performance in suppressing leakage current and enhancing ION current than the SG SOI TFET and DMG TFET. The analytical models of the devices are found to be in good agreement with the results obtained using two-dimensional TCAD device simulator.

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May 2016

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© 2016 Trans Tech Publications Ltd. All Rights Reserved

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[1] Y. Taur and T. H. Ning. Fundamentals of modern VLSI devices. Cambridge: U. K: Cambridge Univ. Press, (1998).

Google Scholar

[2] J. Appenzeller, Y. -M. Lin, J. Knoch, P. Avouris. Band-to-band tunneling in carbon nanotube field-effect transistors. Physics Review Letters, 2004, 93(19): 196.

DOI: 10.1103/physrevlett.93.196805

Google Scholar

[3] K. Boucart, A. M. Ionescu. Double-gate tunnel FET with high-K gate dielectric. IEEE Trans. Electron Devices, 2007, 54(7): 1725.

DOI: 10.1109/ted.2007.899389

Google Scholar

[4] K. K. Bhuwalka, J. Schulze, I. Eisele. Scaling the vertical tunnel FET with tunnel band gap modulation and gate work function engineering. IEEE Trans. Electron Devices, 2005, 52(5): 909.

DOI: 10.1109/ted.2005.846318

Google Scholar

[5] L. Wang, E. Yu, Y. Taur, P. Asbeck. Design of tunneling field effect transistors based on staggered hetero junctions for ultra low power applications. IEEE Electron Device Lett, 2010, 31(5): 431.

DOI: 10.1109/led.2010.2044012

Google Scholar

[6] O. M. Nayfeh, C. N. Chleirigh, J. Hennessy et al. Design of tunneling field-effect transisitors using strained-silicon/strained-germanium type-ii staggered heterojunctions. IEEE Electron Device Lett, 2008, 29(9): 1074.

DOI: 10.1109/led.2008.2000970

Google Scholar

[7] J. Appenzeller, Y. M. Lin, J. Knoch et al. Comparing carbon nanotube transistors - The ideal choice: A novel tunneling device design. IEEE Trans Electron Devices, 2005, 52(12): 2568.

DOI: 10.1109/ted.2005.859654

Google Scholar

[8] K. Boucart, A. M. Ionescu. Double-gate tunnel FET with high- k gate dielectric. IEEE Trans. Electron Devices, 2007, 54(7): 1725.

DOI: 10.1109/ted.2007.899389

Google Scholar

[9] SnehSaurabh, M. Jagadesh Kumar. Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Transactions on Electron Devices, 2011, 58(2): 404.

DOI: 10.1109/ted.2010.2093142

Google Scholar

[10] Min jin Lee. Analytical Model of a single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid-State Electronics, 2011, 63: 110.

DOI: 10.1016/j.sse.2011.05.008

Google Scholar

[11] C. Shen, S. -L. Ong, C. -H. Heng, et al. A variational approach to the two- dimensional nonlinear Poisson's equation for the modeling of tunneling transistors. IEEE Electron Device Lett, 2008, 29(11): 1252.

DOI: 10.1109/led.2008.2005517

Google Scholar

[12] MG. Bardon, HP. Neves, R. Puers et al. Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans., Electron Devices, 2010, 57(4): 827.

DOI: 10.1109/ted.2010.2040661

Google Scholar

[13] A. S. Verhulst, W. G. Vandenberghe, K. Maex et al. Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization. Journal of Applied Physics, 2008, 104(6): 064514.

DOI: 10.1063/1.2981088

Google Scholar

[14] T.S. Arun Samuel, N.B. Balamurugana, S. Bhuvaneswari, et al. Analytical modelling and simulation of single-gate SOI TFET for low-power applications. International Journal of Electronics, 101(6), 779–788, (2014).

DOI: 10.1080/00207217.2013.796544

Google Scholar

[15] T.S. Arun Samuel, N.B. Balamurugan, S. Sibitha et al. Analytical modeling and simulation of dual material gate tunnel field effect transistors. Journal of Electrical Engineering & Technology, 2013, 8(6): 1481.

DOI: 10.5370/jeet.2013.8.6.1481

Google Scholar

[16] E.O. Kane. Zener tunneling in semiconductors. Journal of Physics and Chemistry of Solids, 1960, 12(2): 181.

Google Scholar

[17] E.O. Kane. Theory of tunneling. Journal of Applied Physics, 1961, 32(1); 83.

Google Scholar

[18] Sentaurus Device User Guide, Synopsys Inc., Version D-2010. 03.

Google Scholar