Key Engineering Materials Vol. 1022

Abstract: In our previous work, single-crystalline porous 4H-SiC thin foils were successfully released from a monocrystalline 4H-SiC wafer by photoelectrochemical etching (PECE). This technology is promising for the next-generation power device fabrication processes (e.g. cost-efficient engineered substrates) and micro-electromechanical systems. The surface terminations of the pore walls will affect the behavior in the further fabrication process and application, thus motivating the need for detailed investigations. This work based on DFT calculations focuses on the surface terminations of five 4H-SiC non-polar surfaces, i.e. {10-10}, {11-20}, {21-30}, {31-40} and {32-50}, which can well represent the walls of the C-face etched pores penetrating through the released foil along the [0001] direction. The surface energies of the stoichiometric surfaces are found to be in the sequence of {11-20} < {32-50} < {21-30} < {10-10} < {31-40}. All these surfaces have high chemical affinity to H₂O and even more to HF. In particular, for the complete surface termination by HF, the relative stability of these crystal planes can be changed and depends on the HF chemical potential. For example, in the range of HF chemical potential from −4.10 to −1.70 eV, the 4H-SiC {10-10} becomes more stable than the {11-20}. This preliminary research provides insight into the surface chemistry of the 4H-SiC non-polar surfaces, especially the {21-30}, {31-40} and {32-50}, which have rarely been investigated.

Abstract: We present an accurate calibration strategy for TCAD model parameters of a 1200V vertical Silicon-Carbide (SiC) MOSFET, considering key physical characteristics of SiC such as trap distribution along the SiC/SiO₂ interface, mobility degradation, and Schottky contact for the p-type region. Initially, static characteristics are used to calibrate the SiC/SiO₂ interface traps and mobility model parameters in the low electric field region after matching the simulated doping profile with SIMS. Subsequently, capacitance-voltage (C-V) characteristics are calibrated by considering both the capacitance in periphery and the Schottky effect for the p-type well (PWell) region. Finally, the calibrated model was used to evaluate SC withstand time using mixed-mode TCAD simulation. The simulated static and dynamic performance, including short-circuit (SC) withstand time, are in good agreement to the measurements with an error rate of less than 10%. In summary, we propose a TCAD model parameter calibration method for highly accurate simulation of 1200V vertical SiC MOSFETs, which will contribute to finding process and design solutions that consider both static and dynamic characteristics.

Abstract: Robustness under blocking is an important reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, which typically employs multiple V_DS stress values beyond the rated drain bias but below the avalanche voltage, is considered as the best practice for measuring the device lifetime in the blocking mode. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified modeling approach where qualification-like high temperature reverse bias (HTRB) or ARB test at a single stress voltage for a reasonable stress duration can be used to project gate oxide lifetimes under blocking.