Key Engineering Materials Vol. 1023

Abstract: This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.

Abstract: This study investigates a cost-effective semi-Superjunction (SSJ) solution for 3.3 kV silicon carbide (SiC) MOSFETs, comparing planar and trench configurations. The semi-SJ method, utilizing side-wall implantation and silicon oxide trench refill, offers a practical alternative to the more complex multi-epitaxial growth approach. Through TCAD simulations, the planar semi-SJ MOSFET (planar-SSJ) achieved a 48 % reduction in specific on-state resistance (7.5 mΩ.cm²) and a 4.5 % improvement in maximum blocking voltage (4210 V) compared to conventional planar MOSFET. The trench semi-SJ MOSFET (trench-SSJ), depending on the deep trench angle, can further reduce the specific on-state resistance by 52 % (7.0 mΩ.cm²) and improve the maximum blocking voltage by 6 % (4285 V), while also providing a wider implantation window and a lower gate-oxide electric field.

Abstract: Wide-bandgap silicon carbide (SiC) devices have shown great promise in power control systems due to its high efficiency and thermal stability. However, the absence of predictive compact models for SiC MOSFETs has hindered the validation of these benefits in power electronics applications through circuit simulations. To address this challenge, we introduce a physics-based SPICE model (PbSM) for SiC vertical power MOSFETs. This model is composed of basic subcircuit components that represent various regions in the MOSFET structure, which are physically modeled using a technology computer-aided design (TCAD) tool. By incorporating parasitic resistors into the PbSM, we incorporate the body effect within the MOS channel model with four terminals, thereby enhancing the capability of SPICE simulations. We include theoretical output (C_oss) and reverse transfer capacitances (C_rss) to simulate transient simulations based on a double-pulse test (DPT) setup. SPICE simulation results for static and dynamic characteristics have excellent agreement with the measured characteristics of a SiC MOSFET device, confirming the capability of the model in switching characteristics with voltage distribution across the multiple components. The PbSM shows the impact of parameter variations in switching performance, which promises valuable insights for modeling of the corner cases. Finally, the PbSM is computationally efficient, showing meaningful competitiveness compared to existing SPICE models for SiC power MOSFETs.

Abstract: A novel topological layout was developed to enhance the channel density of 1.2kV 4H-SiC MOSFETs. The innovative "Ladder" MOSFET incorporates an additional JFET and channel region, arranged orthogonally within the layout. To ensure a fair comparison, identical design rules were applied to both the Nominal and Ladder MOSFETs, resulting in calculated channel densities of 0.30 and 0.41, respectively. Comparative analysis was conducted using Synopsys Sentaurus TCAD simulations, where three dimensional (3D) structures for both designs were generated under the same implantation and process conditions, followed by simulations of static electrical characteristics. The results indicate that the Ladder MOSFET achieved approximately 10% reduction in specific on-resistance (R_on,sp) compared to the Nominal MOSFET. Both MOSFET designs were subsequently fabricated, packaged, and evaluated, with the Ladder MOSFET demonstrating a 12.94% reduction in R_on,sp when comparing the best-performing devices from each design.

Abstract: Extensive experiments and simulations indicate that Single-Event ion bombardment Effects (SEE) can trigger a Single-Event Burnout (SEB) in 4H-SiC vertical power devices at lower than half of the rated breakdown voltage. This paper investigates the SEB robustness of a 1.2kV 4H-SiC lateral RESURF MOSFET using a 3-D electrothermal device simulator (Sentaurus) with a reported heavy ion model based on high-fidelity radiation data. The maximum V_SEB/BV_rate ratio of 0.67 is 2.2 times higher than the reported V_SEB/BV_rate ratio of 0.3 for a 4H-SiC vertical DMOSFET with the same voltage rating. The reason is due to the reduced surface field at the drain terminal and the orthogonality of the heavy ion and impact ionization paths, resulting in less efficient excess carrier generation. This highlights the potential of lateral power devices for use in radiation-hardened environments.

Abstract: A set of novel features for the planar gate SiC MOSFETs with the hexagonal unit cell were investigated in terms of the R _DS,ON and reliability (HTRB/HTGB) perspectives. The fabricated SiC MOSFETs with the proposed features improved the R _DS,ON by 9~14% compared to the SiC MOSFETs with the conventional striped unit cell. From the R _DS,ON temperature coefficient perspective (RT Vs. 150°C), the SiC MOSFETs with the proposed features were close to the same counterpart with the marginal difference of ~2%. The SiC MOSFETs with the proposed features showed tighter R _DS,ON and I _D,SS spatial distributions in comparison to the SiC MOSFETs without the proposed features. Two batches of the SiC MOSFETs with select feature were tested for HTRB under the over-stressed conditions. One batch passed the 1,000hr HTRB test and another batch had one I _D,SS failure at 600hr with no further failure up until 1,000hr.

Abstract: With its excellent thermal conductivity, high critical breakdown field strength, and high temperature tolerance, Silicon Carbide (SiC) is widely used in the fabrication of power devices. In recent years, many vertical high-voltage SiC PiN diodes with superior performance have been reported. However, since the cathode-anode voltage in these devices is vertically blocked in the semiconductor, the on-chip isolation between the devices is difficult to achieve. For this reason, the vertical power device is typically employed for high power densities in single-device packages or power modules. In contrast, effective isolation between lateral high-voltage devices can be achieved by using isolation structures, which enables monolithic integration with lateral PiN diodes, transistors, and resistors to achieve control, routing, and power density regulation in smart power-integrated circuits (ICs). This work describes the design and fabrication process of a novel SiC high-voltage lateral PiN (HVLPN) diode with the addition of a lateral isolation structure with a thickness of 10 μm to achieve sufficient isolation between breakdown voltages and devices, as well as a solution for the deep etching of the SiC over 10 μm with a thick enough Hard Mask (HDM), which is required for the actual fabrication process.

Abstract: This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n-channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.

Abstract: Shorter channel-length and thinner gate-oxide are required for the scaling of design pitch and improving device performance. We explored variations in the channel length and gate oxide thickness for 1700 V 4H-SiC based VDMOSFETs. A design of experiments was applied to cover multiple designs and process conditions. The final device results show that the shorter channel with thinner gate-oxide leads to better device performance including lower on-resistance, higher current and transconductance. However, an increase in the device leakage starts affecting the breakdown voltage thus limiting the scaling for given process conditions, such as Pwell and JFET implants.