A Novel 'Ladder' Design for Improved Channel Density for 1.2kV 4H-SiC MOSFETs

Abstract:

A novel topological layout was developed to enhance the channel density of 1.2kV 4H-SiC MOSFETs. The innovative "Ladder" MOSFET incorporates an additional JFET and channel region, arranged orthogonally within the layout. To ensure a fair comparison, identical design rules were applied to both the Nominal and Ladder MOSFETs, resulting in calculated channel densities of 0.30 and 0.41, respectively. Comparative analysis was conducted using Synopsys Sentaurus TCAD simulations, where three dimensional (3D) structures for both designs were generated under the same implantation and process conditions, followed by simulations of static electrical characteristics. The results indicate that the Ladder MOSFET achieved approximately 10% reduction in specific on-resistance (R_on,sp) compared to the Nominal MOSFET. Both MOSFET designs were subsequently fabricated, packaged, and evaluated, with the Ladder MOSFET demonstrating a 12.94% reduction in R_on,sp when comparing the best-performing devices from each design.

• Periodical: Key Engineering Materials (Volume 1023)
• Pages: 21-27
• DOI: https://doi.org/10.4028/p-CF6aix
• Online since: September 2025
• Authors: Skylar de Boer*, Dinuth C.Y.B. Yapa Mudiyanselage, Seung Yup Jang, Adam Morgan, Woong Je Sung
• Keywords: 4H-SiC, Channel Density, Layout Design, MOSFET

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