Key Engineering Materials Vol. 1022

Abstract: 4H-SiC thyristors are of particular interest in pulsed power applications due to their ability to block high voltages and transfer high current densities along with fast switching times. Here, we present a paper that demonstrates both (i) the impact of the design parameters on the blocking characteristics based on simulations taking into account the anisotropy of 4H-SiC and (ii) a critical comparison to real devices having equivalent epitaxial structural design. Simulations and measurements show that an etched junction termination extension (JTE) is suitable to design high-voltage SiC thyristors. Concerning breakdown voltage, the real devices data agree to simulations for junction termination extension thickness in the relevant region. Besides the actual JTE thickness and doping concentration, the presence of a relatively thin field-stop layer might explain the discrepancy between experiment and simulation.

Abstract: There are some technological issues in SiC MOSFETs that are still unsolved. One of the main problems is the high density of traps/defects at the SiC/SiO₂ interface. Traps distribution at such interface is complex and it affects the overall performance of the device. The high-density of defects at the SiC/SiO₂ interface is a relevant problem since it can influence the overall performance of the device, causing detrimental impacts on threshold voltage stability, channel mobility and leakage current amplitude. Due to the fundamental importance of the SiC/SiO₂ interface characterization, several techniques have been employed to investigate defects properties related to this region. In this work non-classical C-V measurements are performed. Capacitance is measured between Gate and Source terminals while a fix DC voltage is imposed on the Drain. This latter is considered among positive values in the first case, while it is chosen as a negative voltage in the second case. The arising capacitances in both cases show an unexpected behavior which can be related to interface properties. To this aim numerical analysis is performed in Sentaurus TCAD environment.

Abstract: Channel mobility is one of the most critical parameters in 4H-SiC based Power MOSFETs and contributes a significant fraction of device on-state resistance. Experimentally, it has been shown that the a-face channel mobility is much higher compared to the Si-face, making a-face a very attractive option for a wide range of applications in the power electronics market. However, modelling of the a-face channel mobility using Technology Computer Aided Design tools is not well established due to the complex nature of channel mobility due to a variety of scattering mechanisms involved. In this paper, we present a well calibrated a-face channel mobility model that shows an excellent match with the available experimental data and further provides critical insights into the anisotropic nature of channel mobility in 4H-SiC MOSFET structures.

Abstract: Power electronics are a key enabling technology in the process towards a fully electrified society. Modern power conversion is integral in delivering efficient electric vehicles (EVs) and their fast charging stations, advanced motor drives and the integration of renewable energy into a modern grid. With an EV market share of 50% targeted by the US Government and the fact that about 50 % of all electricity is used to power and drive electric motors, it becomes evident that efficiency of power electronics systems will be at the center of any policy that wants to steer society towards a more sustainable energy economy.

Abstract: In this paper, the performance in 3^rd quadrant operation of 3^rd and 4^th generation SiC power MOSFETs have been evaluated. These are the Gen-3 1.2 kV & 18 A Planar SiC MOSFET, Gen-3 1.2 kV & 19 A Asymmetrical Trench SiC MOSFET, Gen-4 1.2 kV & 26 A Symmetrical Double-Trench SiC MOSFET and Gen-4 1.2 kV & 19 A Trench-Assisted Planar SiC MOSFET. Further, the transients of early-stage degradation development are investigated by conducting continuous stress current thorough body diode of the aforementioned devices to explore the extent of degradation in the body diodes of SiC MOSFETs. These devices are compared to provide a better understanding of the impact of different structures.

Abstract: This paper presents the development and optimization of a 1.2 kV Silicon Carbide (SiC) Trench MOSFET with a Bottom P-well (BPW), designed to achieve a compact structure and a simplified fabrication process. By performing the BPW implant before the trench etching process and utilizing it in conjunction with a shallow trench, the process complexity was reduced while maintaining effective corner coverage of the trench gate. Comprehensive simulations and unit process analyses were conducted to evaluate the effects of the hard mask sidewall angle, P-well, and JFET implant doses on device characteristics. Optimal performance was achieved by introducing an additional P+ implant in the P-well region, which significantly enhanced breakdown voltage without affecting channel properties. The optimized device demonstrated a specific on-resistance (R_on,sp) of 2.2 mΩ·cm², a breakdown voltage (BV) of 1600 V, and a threshold voltage (V_th) of 3 V, with potential further reductions in R_on,sp through substrate thinning.

Abstract: In this study, we investigated a trench-gate silicon carbide metal-oxide-semiconductor field-effect transistor (SiC-MOSFET) edge-termination structure using an oxide film along the trench surface to simplify the manufacturing process. The trench structure in the termination region serves as a guard ring, eliminating the need for a separate guard ring process and thereby reducing the number of process steps. To suppress electric field concentration at the edge of the cell region under high voltage, a boundary region between the cell and termination regions was implemented. Technology Computer-Aided Design (TCAD) device simulations confirmed that by using the boundary region and narrowing the mesa width, avalanche breakdown was prevented up to the breakdown voltage of the cell region.

Abstract: This paper shows results of SiC Schottky diodes fabricated without ion-implanted P-type regions. Diodes with blocking voltages up to 4,500 V are demonstrated utilizing an epitaxial P-type ring with sloped edges for the edge termination. Reverse-bias currents at temperatures higher than 60°C, and at nominal blocking voltages of 650 V, 1200 V, and 1700 V, are shown to match the theoretical values based on the two fundamental current mechanisms: tunneling and thermionic emission. In comparison to JBS and MPS diodes, the whole anode area is active, which enables homogeneous current flow and comparable isothermal characteristics without the usual wafer thinning. In addition, the non-thinned wafer results in larger thermal capacitance, allowing for higher repetitive peak surge currents for the same junction temperature within the maximum operating temperature of 175°C.

Abstract: We use novel three-level pulse sequences, where the intermediate level is either above or below the threshold voltage, to investigate gate switching instability (GSI) in 4H-SiC-MOSFETs. Results with sequences with an intermediate level above the threshold voltage (V_th) seem to falsify the hypothesis that trapped holes remaining at the interface after switching to the on-state, are the root cause for GSI, as was described in [1, 2]. Fast switching applications may cause negative transient pulses on the gate electrode during the off-state. Results with sequences with an intermediate level below threshold show that such transients may cause an increased V_th-drift. Introducing a delay between the transient and the turn-on of the transistor in such pulse sequences, does not mitigate the effect of a negative transient on the V_th-drift.