Three Level Pulses to Investigate Gate Switching Instability

Abstract:

We use novel three-level pulse sequences, where the intermediate level is either above or below the threshold voltage, to investigate gate switching instability (GSI) in 4H-SiC-MOSFETs. Results with sequences with an intermediate level above the threshold voltage (V_th) seem to falsify the hypothesis that trapped holes remaining at the interface after switching to the on-state, are the root cause for GSI, as was described in [1, 2]. Fast switching applications may cause negative transient pulses on the gate electrode during the off-state. Results with sequences with an intermediate level below threshold show that such transients may cause an increased V_th-drift. Introducing a delay between the transient and the turn-on of the transistor in such pulse sequences, does not mitigate the effect of a negative transient on the V_th-drift.

• Periodical: Key Engineering Materials (Volume 1022)
• Pages: 63-68
• DOI: https://doi.org/10.4028/p-vz2eBi
• Online since: September 2025
• Authors: Dick Scholten*, Juergen Uschmann
• Keywords: 4H-SiC MOSFET, GSI, GSS, Interface Traps, Threshold Voltage, Vth-Drift

References

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