Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Seung Yup Jang; Dong Young Kim; Dinuth C.Y.B. Yapa Mudiyanselage; Ho Jung Lee; Chung Kwang Lee; Jin Gon Kim; Dong Kyun Kim; Woong Je Sung

doi:10.4028/p-Qf5QM9

Paper Titles

SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain
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TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs
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On the Characterization of 4H-SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices
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The 3^rd Quadrant Operation of 4^th Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation
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Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency
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Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film along the Trench Surface
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SiC Schottky-Barrier Diode without Ion-Implanted P-Type Regions
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Three Level Pulses to Investigate Gate Switching Instability
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DFT Calculations on the Termination of 4H-SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation
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HomeKey Engineering MaterialsKey Engineering Materials Vol. 1022Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced...

Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Abstract:

This paper presents the development and optimization of a 1.2 kV Silicon Carbide (SiC) Trench MOSFET with a Bottom P-well (BPW), designed to achieve a compact structure and a simplified fabrication process. By performing the BPW implant before the trench etching process and utilizing it in conjunction with a shallow trench, the process complexity was reduced while maintaining effective corner coverage of the trench gate. Comprehensive simulations and unit process analyses were conducted to evaluate the effects of the hard mask sidewall angle, P-well, and JFET implant doses on device characteristics. Optimal performance was achieved by introducing an additional P+ implant in the P-well region, which significantly enhanced breakdown voltage without affecting channel properties. The optimized device demonstrated a specific on-resistance (R_on,sp) of 2.2 mΩ·cm², a breakdown voltage (BV) of 1600 V, and a threshold voltage (V_th) of 3 V, with potential further reductions in R_on,sp through substrate thinning.

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Periodical:

Key Engineering Materials (Volume 1022)

Pages:

37-43

DOI:

https://doi.org/10.4028/p-Qf5QM9

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Online since:

September 2025

Authors:

Seung Yup Jang*, Dong Young Kim, Dinuth C.Y.B. Yapa Mudiyanselage, Ho Jung Lee, Chung Kwang Lee, Jin Gon Kim, Dong Kyun Kim, Woong Je Sung

Keywords:

4H-Silicon Carbide (SiC), Implantation, Manufacture, MOSFET, Simulation, Trench

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* - Corresponding Author

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