Key Engineering Materials Vol. 1021

Abstract: In this paper, the static and dynamic characterization of a High Voltage (10kV) 4H-SiC Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm^-2. The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV. The study concludes that 4H-SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.

Abstract: We investigated how proton implantation influences electrical characteristics of the 4H-SiC MOSFETs. Bipolar degradation in SiC is one of the key issues to be solved for utilizing the bipolar operation in SiC power devices. Its suppression with the proton implantation technique has recently been reported. If we can apply such a new technique being involved for realizing reliable SiC MOSFETs, it would give us great merit to take advantage of the body diode. However, few study has been reported of proton implanted SiC MOSFETs, to our knowledge. Thus, we fabricated 4,000 chips, applied current stress to their body diodes and subsequently evaluated them to verify statistically any effectiveness on the suppression of the bipolar degradation as well as on the electrical performance of MOSFET in order to consider its technological applicability to their mass production process. We found that proton implantation not only has little influence on the static electrical characteristics of the MOSFETs but also improves the switching characteristics.

Abstract: Silicon Carbide (SiC) is a leading material for power electronics due to its high critical electric field, rapid switching, and high-temperature capabilities. This study delves into the dynamic and thermal performance of a novel SiC power MOSFET, utilizing an innovative vertical Gate All Around (GAA) design. Through detailed 2D TCAD simulations in cylindrical coordinates, the device’s behavior is analyzed across various pillar radii and temperatures. Results indicate that while reducing the pillar radius does not improve the on-resistance (R_ON), a 500 nm radius is required to achieve R_ON < 10 mΩ∙cm². Additionally, larger pillar radii significantly increase capacitance. The device exhibits strong switching performance comparable to commercial counterparts and benefits from the absence of a termination region. However, its short-circuit ruggedness is compromised, particularly in structures with smaller pillar radii, where delayed thermal runaway failure is observed. Notably, for a 20 nm radius, the temperature peak occurs on the Drain side, a deviation from typical behavior. Despite its advantages, the design's low short-circuit capability remains a limitation.

Abstract: The effects of positive and negative high voltage gate stress on the interface trap density and channel conductivity of lateral, Si-face 4H-SiC MOSFETs is studied, and the possible physical mechanisms for interface trap generation are discussed. Charge pumping and I_D-V_GS measurements are used to measure the trap density and field-effect mobility, respectively. The time dependence of the channel degradation is evaluated for different stress voltages with oxide electric field exceeding 8 MV/cm. Positive stress is shown to generate acceptor traps which degrade the field-effect mobility, and the density of traps follows a universal dependence on the injected electron fluence into the gate oxide. In contrast, negative stress resulted in no degradation of the field-effect mobility even as interface trap density increased, indicating that only donor interface traps are created. Furthermore, the trap density during negative stress does not follow a universal dependence on the injected hole fluence, indicating that other mechanisms are responsible for the trap creation.

Abstract: In this work, TCAD simulation of SiC MOSFETs design with deep (2 µm) p-base using single step aluminum channeling implant along [0001] direction and JFET design using phosphorus implant is presented. The threshold voltage (V_th) was around 3 V for both the devices. Improvements to the specific on-resistance (R_on,sp) reduction by ~ 30 %, breakdown voltage (BV) enhancement by ~ 40 %, miller plateau (Q_GD) reduction by ~ 30% is reported. Furthermore, both the Baliga figure-of-merit (BFOM) (BV²/R_on,sp) and high-frequency figure-of-merit (HFOM) (R_on,sp × Q_GD) with 2 µm deep p-base /JFET implant are enhanced as compared to shallow 0.7 µm p-base/JFET implant. This paper provides valuable insights into the advantages of a single-step channeling implant at room temperature, without the need for a hard mask. This approach offers a high throughput with a low-cost process for fabricating high-performance SiC MOSFETs.

Abstract: In this work, we investigate the static electrical parameters of 1200 V 4H-SiC power diodes with various designs and architectures (Schottky, PiN, and JBS with hexagonal or stripes anode), fabricated on two types of 150 mm substrates (single crystal 4H-SiC reference and 3C-poly silicon carbide based substrates: SmartSiC^TM). I(V) measurements are carried out in both reverse and forward modes to assess the impact of designs and substrates. Non-destructive avalanche mode is reached with similar performance (leakage, V_AV) observed for both substrates (due to identical drift layers and device structures). All diode designs on SmartSiC^TM exhibit a larger current conduction and less resistance in the ohmic regime (compared to bulk), whatever the temperature (up to 200°C). Partitioning model is also proposed for evaluating the substrate contribution on the measured specific resistance and on the observed SmartSiC^TM gains.

Abstract: This paper investigates the charge balancing and performance optimization of two 1.2 kV rated Semi-Superjunction (SSJ) MOSFETs. Beginning with a conventional double trench MOSFET, SJ trenches are imposed in 2D (within the X-Y plane unit cell) and in 3D (trenches in Z-Y plane, perpendicular to the gate trench). The optimization of these structures focuses on the effects of p-pillar doping, tilt angle, and z-plane pillar width and the trade-off between specific on-resistance R_on,sp, breakdown voltage (BV), implantation window, and gate reliability is assessed for each configuration. The 2D SSJ MOSFET, is the device that offers the highest breakdown voltage of those assessed (1781 V) and the widest implantation window (±25.4%), when implemented with a vertical trench sidewall, while this is a trade-off against achieving the lowest R_on,sp​, (1.15 mΩ.cm²) with a 12.5° side wall angle. In the 3D SSJ MOSFET, a reduced p-pillar depth in the z-dimension, and hence a higher doping density, leads to a significant improvement in R_on,sp. The Z-plane p-pillars in the 3D device efficiently deplete its JFET region, causing the R_on,sp of the 3D devices to be higher than the 2D devices, and the breakdown voltage lower. However, this also results in very low electric field (<0.5 MV/cm), in the gate oxide, offering a safe alternative to the 2D devices (1.69 MV/cm). Differences between the devices could be narrowed in the future with optimal JFET design.

Abstract: A novel substrate of 4H-SiC bonded substrate is expected to solve issues such as decreasing the on-resistance, which has attracted much attention. Therefore, several studies have been conducted on the use of bonded substrates. In this study, we fabricated a DMOSFET on a bonded substrate and compared its static and dynamic characteristics with those on a single-crystal substrate. Consequently, the on-resistance of the DMOSFET fabricated on a bonded substrate was lower than that on a single-crystal substrate owing to the low resistivity of the polycrystalline substrate. Also, reverse recovery loss of the DMOSFET fabricated on a bonded substrate was lower than that on single-crystal substrate at high temperature due to low carrier lifetime in a drift layer. Additionally, we observed that the DMOSFET fabricated on a bonded substrate did not generate bipolar degradation despite the application of a forward-current stress of over 1500 A cm^-2. According to these results, we expected that the carrier lifetime in both drift layer and transfer layer was decreased on a bonded substrate.

Abstract: We experimentally demonstrated >2.5x on-current improvement on VDMOSFET fabricated in a standard 1200 V-rated 4H-SiC based VDMOSFET. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A >10⁴ ratio between the on-current gain and the p-well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.