Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Pavan Vudumula; Yu Chieh Chien; Abdul Hannan Yeo; Lakshmi Kanta Bera; Umesh Chand; Voo Qin Gui Roth; Surasit Chung; Navab Singh; Yee Chia Yeo

doi:10.4028/p-4QkAFT

Paper Titles

Electrical Characterization of HV (10 Kv) Power 4H-SiC Bipolar Junction Transistor
p.1

Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-Sic MOSFET
p.7

Evaluation of Switching Performances and Short Circuit Capability of a 1.2 kV SiC GAA MOSFET through TCAD Simulations
p.17

Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs
p.25

Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET
p.35

Temperature Dependence of 1200V-10A SiC Power Diodes Impact of Design and Substrate on Electrical Performance
p.41

Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization
p.51

Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate
p.59

1200 V 4H-SiC VDMOSFET Having > 2.5x On-Current Improvement
p.69

HomeKey Engineering MaterialsKey Engineering Materials Vol. 1021Impact of Single-Step Deep P-Body Implant on 1.2...

Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Abstract:

In this work, TCAD simulation of SiC MOSFETs design with deep (2 µm) p-base using single step aluminum channeling implant along [0001] direction and JFET design using phosphorus implant is presented. The threshold voltage (V_th) was around 3 V for both the devices. Improvements to the specific on-resistance (R_on,sp) reduction by ~ 30 %, breakdown voltage (BV) enhancement by ~ 40 %, miller plateau (Q_GD) reduction by ~ 30% is reported. Furthermore, both the Baliga figure-of-merit (BFOM) (BV²/R_on,sp) and high-frequency figure-of-merit (HFOM) (R_on,sp × Q_GD) with 2 µm deep p-base /JFET implant are enhanced as compared to shallow 0.7 µm p-base/JFET implant. This paper provides valuable insights into the advantages of a single-step channeling implant at room temperature, without the need for a hard mask. This approach offers a high throughput with a low-cost process for fabricating high-performance SiC MOSFETs.

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Periodical:

Key Engineering Materials (Volume 1021)

Pages:

35-39

DOI:

https://doi.org/10.4028/p-4QkAFT

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Online since:

September 2025

Authors:

Pavan Vudumula, Yu Chieh Chien, Abdul Hannan Yeo*, Lakshmi Kanta Bera, Umesh Chand, Voo Qin Gui Roth, Surasit Chung, Navab Singh, Yee Chia Yeo

Keywords:

Channeling Implant, Deep P-Body, Single Step Implant

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* - Corresponding Author

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