Optimal Structural Design of Multi Chip Package to Reduce the Failure in Substrate

Abstract:

In this study, epoxy molded multi chip package was investigated and a highly reliable structure against failure of copper trace on PCB substrate was proposed. Function failure caused by the pattern crack during component level thermal cycle test was considered. In-plane and out-of-plane movements of package during thermal loading were measured by moiré interferometry and shadow moiré. Measured data were compared with numerical analysis results. Two dimensional and three dimensional numerical analysis were performed considering visco-elastic material properties. Tensile stress in the core layer was analyzed quantitatively and qualitatively. Analysis showed that the reliability of pattern crack could be improved by decreasing the chip thickness and increasing the core thickness, and that the material property of die adhesive was important.

• Periodical: Key Engineering Materials (Volumes 297-300)
• Pages: 912-917
• DOI: https://doi.org/10.4028/www.scientific.net/KEM.297-300.912
• Online since: November 2005
• Authors: Dong Kil Shin, Seung Woo Kim, Shin Kim, Seok Won Lee, Hee Kook Choi
• Keywords: Finite Element Analysis (FEA), Moiré Interferometry, Multi Chip Package, Shadow Moiré, Visco Elasticity

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