CMOS Amplifier for Neural Signal Recording Applications

Article Preview

Abstract:

A low power low noise CMOS amplifier with integrated filter for neural signal recording is designed and fabricated with CSMC 0.5 μm CMOS process. DC offsets introduced by electrode-tissue interface are rejected through a feedback low-pass filter. The bandwidth of the amplifier is in 3.5Hz-5.5KHz range, and the gain is about 48dB in the midband. AC input differential mode voltage range is 10mV, and DC input differential mode voltage range is 180mV. The amplifier can accommodate 180mV DC offsets drift and 10mV neural spikes. The neural probe array is integrated directly on the surface of the amplifier array chip, and is tested in saline solution, and also is implanted in rats in vivo , the results of the experiments show that the amplifier is suitable for neural signal recording. The power dissipation is about 14μW while consuming 0.16 mm2 of chip area, which satisfies implantable devices requirements.

You might also be interested in these eBooks

Info:

Periodical:

Key Engineering Materials (Volumes 645-646)

Pages:

1279-1284

Citation:

Online since:

May 2015

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2015 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] K. D. WISE, D. J. ANDERSON, J. F. HETKE, D. R. KIPKE, AND K. NAJAFI, Wireless Implantable Microsystems: High-Density Electronic Interfaces to the Nervous System, IEEE PROCEEDINGS OF THE IEEE. 92, ( 2004)76-97.

DOI: 10.1109/jproc.2003.820544

Google Scholar

[2] Reid R. Harrison, the design of integrated circuits to observe brain activity, Proceedings of the IEEE. 96, (2008) 1203-1216.

DOI: 10.1109/jproc.2008.922581

Google Scholar

[3] Reid R. Harrison, Cameron Charles, a low-power low-noise CMOS amplifier for neural recording applications, IEEE journal of solid-state circuits. 38(2003)958-965.

DOI: 10.1109/jssc.2003.811979

Google Scholar

[4] Yoon-Kyu Song, William R. Patterson, Christopher W. Bull, et al, Development of a chipscale Integrated Microelectrode/Microelectronic device for Brain Implantable Neuroengineering Applications. 13, (2005)220-226.

DOI: 10.1109/tnsre.2005.848337

Google Scholar

[5] Qing Bai, Kensall D. Wise, single-unit neural recording with active microelectrode arrays, IEEE transactions on biomedical engineering. 48, (2001) 911-920.

DOI: 10.1109/10.936367

Google Scholar

[6] Jin Ji, Kensall D. Wise, An Implantable CMOS Circuit Interface for Multiplexed Microelectrode Recording Arrays, IEEE Journal of solid-state circuits. 27(1992)433-443.

DOI: 10.1109/4.121568

Google Scholar

[7] Zhuang Yiwei, Cheng Zhengxi, Zhang Xueming, Yuan Honghui, Fabricaiton of the silicon-based three-dimension neural probe arrays, Key Engineering Materials. 609-610(2014)758-768.

DOI: 10.4028/www.scientific.net/kem.609-610.758

Google Scholar

[8] Cheng Zhengxi, Zhuang Yiwei, et al, Fabrication of Hybrid Three Dimension Neural Probe Arrays, Chinese Journal of sensors and actuators. 26(2013)150-156.

Google Scholar