For Libraries For Publication Open Access Downloads About Us Contact Us
Paper Titles
Impact of Notch Structures on Transfer Characteristics of AlGaN/GaN HEMTs: A Simulation Study
p.15
Comparison of the Electrical Performance of AlN and HfO2 Passivation Layer in AlGaN/GaN HEMT
p.21
Microfiber Optics Liquid Refractometer: The Effect of Taper Waist
p.27
Temperature Dependence of Electrical Characteristics of ZnO Nanowire Field-Effect Transistors with AZO and Aluminium Source/Drain Contact
p.33
Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness
p.39
Investigation on Absorption and Photocurrent in Silicon Absorber with Varied Pyramid Texture Angles by Ray Tracer
p.47
Threshold Voltage Adjustment on 4H-SiC MOSFETs Using P-Doped Polysilicon as a Gate Material
p.57
Demonstration of SiC Trench Gate MOSFETs with Narrow Cell Pitch Using Source Self-Aligned Process
p.63
Assessing, Controlling and Understanding Parameter Variations of SiC Power MOSFETs in Switching Operation
p.69

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Article Preview

Abstract:

Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

You might also be interested in these eBooks
2nd International Conference on Semiconductor Materials and Technology (ICoSeMT 2021) View Preview
Engineering Materials: Research and Application Optimization View Preview

Info:

Periodical:

Key Engineering Materials (Volume 947)

Pages:

39-45

DOI:

https://doi.org/10.4028/p-3a337l

Citation:

Cite this paper

Online since:

May 2023

Authors:

Siti NorFarah Nadia Mohd Salleh, Alhan Farhanah Abd Rahim*, Nurul Syuhadah Mohd Razali, Rosfariza Radzali, Ainorkhilah Mahmood, Irni Hamiza Hamzah

Keywords:

Drain Current, Ge Composition, MOSFET, Strained-SiGe, TCAD Modeling

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

© 2023 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

References

[1] S.R. Sriram, B. Bindu, Hot Carrier Reliability in 45 nm Strained Si/relaxed Si1−xGex CMOS Based SRAM Cell, 2018 15th IEEE India Council International Conference (INDICON), 2018, pp.1-6.

DOI: 10.1109/indicon45594.2018.8987152

Google Scholar

[2] D. Mohanta, S.S. Singh, Study of Electrical Parameters of Strained Si PMOS with High k Dielectric Material Using TCAD, 2022 IEEE VLSI Device Circuit and System (VLSI DCS), 2022, pp.244-247.

DOI: 10.1109/vlsidcs53788.2022.9811476

Google Scholar

[3] K. Arimoto, T. Fujisawa, D. Namiuchi, A. Onogawa, Y. Sano, D. Izumi, J. Yamanaka, K.O. Hara, K. Sawano, K. Nakagawa, Dependences of the hole mobility in the strained Si pMOSFET and gated Hall bars formed on SiGe/Si(110) on the channel direction and the strained Si thickness, Journal of Crystal Growth 571 (2021) 126246.

DOI: 10.1016/j.jcrysgro.2021.126246

Google Scholar

[4] T. Bentrcia, F. Djeffal, M. Chahdi, Performance evaluation of nanoscale halo dual-material double gate SiGe MOSFET using 2-D numerical simulation, Materials Today: Proceedings 20 (2020) 348-355.

DOI: 10.1016/j.matpr.2019.10.073

Google Scholar

[5] A.F. Abd Rahim, N.S.I. Mohamad Shuhaimi, N.S. Mohd Razali, R. Radzali, A. Mahmood, I.H. Hamzah, M.F. Mohamed Packeer, Dimensional effect of doped porous Ge using SILVACO TCAD simulation for potential optoelectronics application, ESTEEM Academic Journal 17 (2021) 78-88.

DOI: 10.17576/jsm-2022-5112-17

Google Scholar

[6] K.S.K. Kwa, S. Chattopadhyay, S.H. Olsen, L.S. Driscoll, A.G.O. Neill, Optimisation of channel thickness in strained Si/SiGe MOSFETs, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003., 2003, pp.501-504.

DOI: 10.1109/essderc.2003.1256923

Google Scholar

[7] P. Hashemi, T. Ando, K. Balakrishnan, S. Koswatta, L. Kam-Leung, J.A. Ott, K. Chan, J. Bruley, S.U. Engelmann, V. Narayanan, E. Leobandung, R.T. Mo, High performance PMOS with strained high-Ge-content SiGe fins for advanced logic applications, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, pp.1-2

DOI: 10.1109/vlsi-tsa.2017.7942468

Google Scholar

[8] A. M. Taberkit, A. Guen-Bouazza, M. Horch, The importance of using dual channel heterostructure in strained P-MOSFETs, 2018 International Conference on Communications and Electrical Engineering (ICCEE), 2018, pp.1-5.

DOI: 10.1109/ccee.2018.8634492

Google Scholar

[9] L. Gomez, P. Hashemi, J.L. Hoyt, Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs, IEEE Transactions on Electron Devices 56(11) (2009) 2644-2651.

DOI: 10.1109/ted.2009.2031043

Google Scholar

[10] S.S. Mahato, A.R. Saha, Reliability Issues in strained-Si MOSFETs, IETE Journal of Research 53(3) (2007) 277-284.

DOI: 10.1080/03772063.2007.10876141

Google Scholar

[11] A. Kumari, S. Kumar, Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp.427-432.

DOI: 10.1109/vlsid.2014.80

Google Scholar

[12] A.F. Abd Rahim, N.Z. Baharom, R. Radzali, A. Mahmood, M. Mohamed Zahidi, M. Jumidali, Low Dimensional Ge Island on Si for Visible Metal-Semiconductor-Metal Photodetector, ESTEEM Academic Journal 14 (2018) 1-11.

DOI: 10.1051/epjconf/201716201062

Google Scholar

[13] I. Aberg, C. Cait Ni, J.L. Hoyt, Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs, IEEE Transactions on Electron Devices 53(5) (2006) 1021-1029.

DOI: 10.1109/ted.2006.871847

Google Scholar

[14] G.K. Dalapati, S. Chattopadhyay, K.S.K. Kwa, S.H. Olsen, Y.L. Tsang, R. Agaiby, A.G.O. Neill, P. Dobrosz, S.J. Bull, Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs, IEEE Transactions on Electron Devices 53(5) (2006) 1142-1152.

DOI: 10.1109/ted.2006.872086

Google Scholar

[15] D.J. Paul, Si/SiGe heterostructures: from material and physics to devices and circuits, Semiconductor Science and Technology 19(10) (2004) R75-R108.

DOI: 10.1088/0268-1242/19/10/r02

Google Scholar

[16] I. Saad, B.S. Chan, M.Z. Hamzah, N. Bolong, K.A. Mohamad, Breakdown Voltage Reduction Analysis with Adopting Dual Channel Vertical Strained SiGe Impact Ionization MOSFET (VESIMOS), International Journal of Simulation- Systems, Science and Technology- IJSSST 15(2) (2014) 40-45

DOI: 10.5013/ijssst.a.15.02.06

Google Scholar

[17] M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, S. Nakamura, <100> channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, pp.94-95.

DOI: 10.1109/vlsit.2002.1015403

Google Scholar

[18] M.J. Kumar, V. Venkataraman, S. Nawal, Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs, IEEE Transactions on Device and Materials Reliability 7(1) (2007) 181-187.

DOI: 10.1109/tdmr.2006.889269

Google Scholar

[19] C.N. Chleirigh, N.D. Theodore, H. Fukuyama, S. Mure, H. Ehrke, A. Domenicucci, J.L. Hoyt, Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs, IEEE Transactions on Electron Devices 55(10) (2008) 2687-2694.

DOI: 10.1109/ted.2008.2003228

Google Scholar

[20] C. Vedatrayee, B. Mukhopadhyay, P.K. Basu, A compact drift-diffusion current model of strained-Si-Si1-xGex MOSFETs, 2009 4th International Conference on Computers and Devices for Communication (CODEC), 2009, pp.1-4.

Google Scholar

© 2025 Trans Tech Publications Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies. For open access content, terms of the Creative Commons licensing CC-BY are applied.
Scientific.Net is a registered trademark of Trans Tech Publications Ltd.