High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs

Abstract:

In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO₂) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (V_G SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the V_G SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

• Periodical: Materials Science Forum (Volume 1004)
• Pages: 1033-1044
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.1004.1033
• Online since: July 2020
• Authors: Elena Mengotti*, Enea Bianda, Stephan Wirths, David Baumann, Jason Bettega, Joni Jormanainen
• Keywords: Extrinsic, Gate Oxide, Intrinsic, Planar, Reliability, SiC-MOSFET, Testing, Trench

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