Influence of Shallow Pits and Device Design of 4H-SiC VDMOS Transistors on In-Line Defect Analysis by Photoluminescence and Differential Interference Contrast Mapping

Matthias Kocher; Holger Schlichting; Birgit Kallinger; Mathias Rommel; Anton J. Bauer; Tobias Erlbacher

doi:10.4028/www.scientific.net/MSF.1004.299

Paper Titles

Resistivity Measurement of P⁺-Implanted 4H-SiC Samples Prepared at Different Implantation and Annealing Temperatures Using Terahertz Time-Domain Spectroscopic Ellipsometry
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Investigation of the Influence of Structural Defects on the PL Spectra in n-3C-SiC
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Quantitative Characterization of Surface Polarity Dependence of Wetting Properties of V-Doped SiC Using a Novel Image Analysis Technique
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Interest of Using a Micro-Meter Spatial Resolution to Study SiC Semi-Conductor Devices by Optical Beam Induced Current (OBIC)
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Influence of Shallow Pits and Device Design of 4H-SiC VDMOS Transistors on In-Line Defect Analysis by Photoluminescence and Differential Interference Contrast Mapping
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A New Technique for Analyzing Defects in Silicon Carbide Devices: Electrically Detected Electron Nuclear Double Resonance
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Review and Detail Classification of Stacking Faults in 4H-SiC Epitaxial Layer by Mirror Projection Electron Microscopy
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From Wafers to Bits and Back again: Using Deep Learning to Accelerate the Development and Characterization of SiC
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Current-Mode Deep Level Spectroscopy of Vanadium-Doped HPSI 4H-SiC
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Influence of Shallow Pits and Device Design of 4H-SiC VDMOS Transistors on In-Line Defect Analysis by Photoluminescence and Differential Interference Contrast Mapping

Abstract:

In this study, UV Photoluminescence (UVPL) and Differential Interference Contrast (DIC) mapping was applied for process control of a 1.2 kV 4H-SiC VDMOS fabrication process at different process stages in order to investigate the influence of shallow pits on the electrical behavior of the devices. In particular, it could be shown that UVPL and DIC mapping allows the correlation of shallow pits and the occurrence of darker regions in the UVPL images and distinguishing differently implanted regions at distinct process stages. By comparing the darker regions of the UVPL scan with the electrical blocking characteristics of the associated devices a direct correlation between the occurrence of shallow pits and the reduction of the blocking capability of the devices could be observed.

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Periodical:

Materials Science Forum (Volume 1004)

Pages:

299-305

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.1004.299

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Online since:

July 2020

Authors:

Matthias Kocher*, Holger Schlichting, Birgit Kallinger, Mathias Rommel, Anton J. Bauer, Tobias Erlbacher

Keywords:

Differential Interference Contrast, Photoluminescence, VDMOS, Yield

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