Materials Science Forum Vol. 1158

Abstract: This study investigates the interface and reliability of metal-oxide-semiconductor capacitors (MOSCAPs) based on 3C-SiC and 4H-SiC using atomic layer deposition (ALD) and post-deposition annealing (PDA). SiO₂ and HfO₂/SiO₂ were used as dielectric layers, with systematic PDA treatments conducted at 600°C, 900°C, and 1100°C in N₂ or forming gas (FG, a mixture of H₂ and N₂) environments to evaluate the impact of the PDA conditions on the interface characteristics of SiC MOSCAPs. The flat-band voltage for 3C-SiC MOSCAPs averaged at 0.68 ± 0.05 V for SiO₂/3C-SiC/Si samples and 2.35 ± 0.01 V for HfO₂/SiO₂/3C-SiC samples when MOSCAPs annealed at 1100°C in FG. PDA in forming gas also significantly reduced hysteresis, dropping from 1.75 V to 0.18 V for SiO₂/3C-SiC and from 2.49 V to 0.04 V for HfO₂/SiO₂/3C-SiC samples. For 4H-SiC MOSCAPs, as-deposited devices exhibited high oxide charges and poor interface quality. The average flat-band voltages for SiO₂/4H-SiC were 9.01 ± 0.15 V, while HfO₂/SiO₂ MOSCAPs showed 6.65 ± 0.02 V. After PDA at 1100°C, the flat-band voltage improved to-0.65 ± 0.035 V for SiO₂/4H-SiC and-0.50 ± 0.05 V for HfO₂/SiO₂/4H-SiC. Additionally, hysteresis was reduced from 0.61 V to 0.15 V for SiO₂/4H-SiC and from 0.23 V to 0.05 V for HfO₂/SiO₂/4H-SiC samples. We propose a figure of merit (FOM) which is defined as the ratio of the breakdown field to the product of flatband voltage shift, hysteresis effect, and density of interface states. The results demonstrate that PDA significantly enhances the interface quality and electrical characteristics of the MOS capacitors (MOSCAPs), with nitrogen (N₂) PDA yielding higher FOM for 4H-SiC stacks and forming FG PDA showing superior interfacial quality for 3C-SiC stacks.

Abstract: GE Aerospace is developing a novel fabrication method for >3.3 kV devices using ultra-high energy deep implantation and epitaxial overgrowth. We report succesful fabrication of the world’s first 3.5 kV SiC SJ deep implanted junction barrier Schottky (JBS) diodes and 5 kV SiC SJ deep implanted MOSFETs, which exhibit record low specific on-resistance (Ron,sp) and superior breakdown voltages. This innovative method offers a scalable path towards more efficient medium-voltage converters, outperforming traditional SiC unipolar devices.

Abstract: Trench filling epitaxy on 4HSiC using trichlorosilane (HSiCl₃) and hydrogen chloride (HCl) has shown to improve the tolerance to trench angle misalignment relative to the substrate direction in deeper trenches than previously reported. Extraction of growth rates from crosssectional SEM shows that epilayer growth on the mesa corner facet is the most sensitive to trench misalignment, suggesting that HCl may mediate the facet growth rate within ±1.5º from to maintain symmetric growth.

Abstract: We have successfully demonstrated comprehensive trench etching of 4H-SiC across various crystal orientations. The results show that both the trench profile and etching depth are unaffected by changes in crystal plane orientation. We achieved our target trench etching depth of 1.9 µm, with vertical sidewall profile angles ranging from 87º to 90º for different crystal planes. Additionally, we performed a qualitative analysis of sidewall roughness for various crystal planes using a 3DAFM scan. It was observed that crystal angles from-60º to-90º exhibited lower surface roughness. We have also explained the mechanisms associated with these surface roughness characteristics.