Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Article Preview

Abstract:

This study investigates the interface and reliability of metal-oxide-semiconductor capacitors (MOSCAPs) based on 3C-SiC and 4H-SiC using atomic layer deposition (ALD) and post-deposition annealing (PDA). SiO2 and HfO2/SiO2 were used as dielectric layers, with systematic PDA treatments conducted at 600°C, 900°C, and 1100°C in N₂ or forming gas (FG, a mixture of H2 and N2) environments to evaluate the impact of the PDA conditions on the interface characteristics of SiC MOSCAPs. The flat-band voltage for 3C-SiC MOSCAPs averaged at 0.68 ± 0.05 V for SiO2/3C-SiC/Si samples and 2.35 ± 0.01 V for HfO2/SiO2/3C-SiC samples when MOSCAPs annealed at 1100°C in FG. PDA in forming gas also significantly reduced hysteresis, dropping from 1.75 V to 0.18 V for SiO2/3C-SiC and from 2.49 V to 0.04 V for HfO2/SiO2/3C-SiC samples. For 4H-SiC MOSCAPs, as-deposited devices exhibited high oxide charges and poor interface quality. The average flat-band voltages for SiO2/4H-SiC were 9.01 ± 0.15 V, while HfO2/SiO2 MOSCAPs showed 6.65 ± 0.02 V. After PDA at 1100°C, the flat-band voltage improved to-0.65 ± 0.035 V for SiO2/4H-SiC and-0.50 ± 0.05 V for HfO2/SiO2/4H-SiC. Additionally, hysteresis was reduced from 0.61 V to 0.15 V for SiO2/4H-SiC and from 0.23 V to 0.05 V for HfO2/SiO2/4H-SiC samples. We propose a figure of merit (FOM) which is defined as the ratio of the breakdown field to the product of flatband voltage shift, hysteresis effect, and density of interface states. The results demonstrate that PDA significantly enhances the interface quality and electrical characteristics of the MOS capacitors (MOSCAPs), with nitrogen (N2) PDA yielding higher FOM for 4H-SiC stacks and forming FG PDA showing superior interfacial quality for 3C-SiC stacks.

You have full access to the following eBook

Info:

* - Corresponding Author

[1] Eea, "Transport and environment report 2022 - Digitalisation in the mobility system: challenges and opportunities,".

Google Scholar

[2] X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, "Review of Silicon Carbide Power Devices and Their Applications," IEEE Transactions on Industrial Electronics, vol. 64, no. 10, p.8193–8205, Oct. 2017.

DOI: 10.1109/TIE.2017.2652401

Google Scholar

[3] C. Langpoklakpam et al., "Review of Silicon Carbide Processing for Power MOSFET," Feb. 01, 2022, MDPI.

DOI: 10.3390/cryst12020245

Google Scholar

[4] A. Siddiqui, R. Y. Khosa, and M. Usman, "High-k dielectrics for 4H-silicon carbide: present status and future perspectives," Apr. 21, 2021, Royal Society of Chemistry.

DOI: 10.1039/d0tc05008c

Google Scholar

[5] P. Fiorenza, F. Giannazzo, and F. Roccaforte, "Characterization of SiO2/4H-SiC interfaces in 4H-SiC MOSFETs: A review," 2019, MDPI AG

DOI: 10.3390/en12122310

Google Scholar

[6] S. T. Pantelides et al., "Si/SiO2 and SiC/SiO2 Interfaces for MOSFETs – Challenges and Advances," Materials Science Forum, vol. 527–529, p.935–948, Oct. 2006.

DOI: 10.4028/www.scientific.net/msf.527-529.935

Google Scholar

[7] K. Zekentes and K. Vasilevskiy, "Advancing Silicon Carbide Electronics Technology II Core Technologies of Silicon Carbide Device Processing," 2020. [Online]. Available: http://www.mrforum.com

DOI: 10.21741/9781945291852

Google Scholar

[8] A. B. Renz et al., "Development of high-quality gate oxide on 4H-SiC using atomic layer deposition," in Materials Science Forum, Trans Tech Publications Ltd, 2020, p.547–553.

DOI: 10.4028/www.scientific.net/MSF.1004.547

Google Scholar

[9] G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-κ gate dielectrics: Current status and materials properties considerations," J Appl Phys, vol. 89, no. 10, p.5243–5275, May 2001.

DOI: 10.1063/1.1361065

Google Scholar

[10] S. Tanimoto, "Highly reliable SiO2/SiN/SiO2(ONO) gate dielectric on 4H-SiC," Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), vol. 90, no. 5, p.1–10, May 2007.

DOI: 10.1002/ecjb.20329

Google Scholar

[11] T. Hosoi et al., "AlON/SiO2 stacked gate dielectrics for 4H-SiC MIS devices," in Materials Science Forum, Trans Tech Publications Ltd, 2009, p.541–544.

DOI: 10.4028/www.scientific.net/MSF.615-617.541

Google Scholar

[12] H. Watanabe et al., " (Invited) Impact of Stacked AlON/SiO 2 Gate Dielectrics for SiC Power Devices ," ECS Trans, vol. 35, no. 2, p.265–274, Apr. 2011.

DOI: 10.1149/1.3568869

Google Scholar

[13] A. B. Renz et al., "Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications," Semicond Sci Technol, vol. 36, no. 5, May 2021.

DOI: 10.1088/1361-6641/abefa1

Google Scholar

[14] G. Colston et al., "Three-Dimensional Epitaxy of Low-Defect 3C-SiC on a Geometrically Modified Silicon Substrate," Materials, vol. 17, no. 7, Apr. 2024.

DOI: 10.3390/ma17071587

Google Scholar

[15] F. Li, S. Qiu, M. Jennings, and P. Mawby, "Reliability study of mos capacitors fabricated on 3c-sic/si substrates," in Materials Science Forum, Trans Tech Publications Ltd, 2020, p.659–664.

DOI: 10.4028/www.scientific.net/MSF.1004.659

Google Scholar

[16] A. Schöner, M. Krieger, G. Pensl, M. Abe, and H. Nagasawa, "Fabrication and characterization of 3C-SiC-based MOSFETs," Chemical Vapor Deposition, vol. 12, no. 8–9, p.523–530, Aug. 2006.

DOI: 10.1002/cvde.200606467

Google Scholar