Materials Science Forum Vol. 1158

Abstract: In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and 1700-V VDMOSFET devices on a single 4H-SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reach-through in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV, was then conducted to verify the breakdown voltage (V_BD) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (V_BD) exceeding 2000 V.

Abstract: The impact of silicon nitride (Si₃N₄) stress on 4H-SiC has been investigated. Current-voltage (I-V) measurements on Schottky barrier diode show that Si₃N₄ films thicker than 100 nm degrade both the ideality factor and Schottky barrier height. A 45-nm sacrificial oxidation effectively reduces defects from a 100-nm-thick Si₃N₄ layer, but defects persist with films over 300 nm. Interface state density of metal oxide semiconductor capacitor with a 44-nm-thick gate oxide confirms the effectiveness of sacrificial oxidation in mitigating defects.

Abstract: This study investigates the role of the electrical failure of the SiO₂ film in the breakdown of SiO₂/ZrO₂ and SiO₂/HfO₂ stacks. Our findings indicate that the breakdown is governed by the SiO₂ film, regardless of its thickness. This highlights the importance of carefully considering the interfacial SiO₂ layer when using high-k materials in SiC devices. We demonstrate that thicker SiO₂ layers offer several benefits, including reduced leakage, enhanced thermal stability and electrical strength, and decreased trapping. In contrast, stacks with thinner SiO₂ have a higher effective k value, exploiting the benefits of high-k dielectrics. Our experimental results suggest that a 7 nm SiO₂ layer underlying 30 nm crystalline ZrO₂ or HfO₂ provides optimal performance. Furthermore, we present calculations that reveal the trade-off between SiO₂ thickness, k value, and breakdown voltage for a 50 nm thick dielectric stack. Our results imply that a k value exceeding 20 does not yield significant benefits in 50 nm thick SiO₂/dielectric stacks.

Abstract: In this work, we investigated the electrical properties evolution of Mo/4H-SiC Schottky contacts following thermal annealing treatments at temperature up to 950 °C. The electrical characterization under forward and reverse bias revealed a reduction of the barrier height from 1.45 eV (as-deposited contact) to 1.30 eV (950°C-annealed contact), with the presence of inhomogeneity in the contact, while the leakage current followed a thermionic-field emission (TFE) model after annealing at 750 °C and presented a significant increase for the 950°C-annealed contact. The electrical characterization was associated with microstructural analyses, which highlighted an enlargement of the grains forming the structure of the Mo-film and the presence of voids near the Mo/4H-SiC interface. These observations can be at the base of the variation in the electrical behavior of the contact.

Abstract: This paper explains the potential of a heat conduction based RTA (Rapid Thermal Anneal) system (Levo) to overcome the main shortcomings of conventional lamp heated tools systems for silicide top contact anneal during SiC MOSFET device fabrication. The advantage of conductive heating is that the radiation-related properties, like transparency of the wafer, does not play a role, and consequently, that the whole rapid thermal anneal becomes independent of wafer type. In this study SiC wafers and Si wafers (both 200mm) were annealed consecutively without any system adjustment. The silicon wafers were used to qualify the process (contamination / within-wafer uniformity and wafer-to-wafer repeatability).

Abstract: This study investigates the effects of lower pressure and chlorine gas added oxidation on the GOI during the SiC MOSFET GOX process. For structural comparison, analyses were conducted using Dynamic SIMS and TOF-SIMS. Notable differences in the uniformity of silicon concentration within the oxide layer were observed under various GOX conditions. To evaluate the impact of these differences on the characteristics of SiC MOSFETs, Q_BD results were compared. To enhance the reliability of the findings, DOE evaluations of GOX were performed across multiple products. The experimental results indicated that the SiC MOSFET wafers subjected to chlorine oxidation exhibited improved Q_BD performance compared to other conditions.

Abstract: To ensure maximum device current is supplied through a vertical device having a backside ohmic contact, the specific contact resistivity, ρ_c, must be well characterized as it constitutes a portion of the device resistance. While there are multiple approaches to deduce ρ_c, the transmission line model (TLM) remains a convenient choice because of its simplicity in terms of fabrication, measurement, and analysis. For thick substrates where mesa isolation is impractical, the circular transmission line model (CTLM) is an attractive path. In this study we propose an additional restriction on the CTLM design such that the ρ_c is readily extracted from a simple linear regression just as is the case in a linear TLM. We demonstrate the simplified method by extracting ρ_c of an ohmic contact to the c-face of 4H-SiC substrate.

Abstract: Heavily p-type doped (P⁺) implants are commonly used to achieve low specific contact resistance (SCR) for p-body diodes through a costly ion implantation process. Alternatively, our study proposes a single-step plasma treatment method using BCl₃ plasma. This method incorporated a high concentration of self-activated p-type boron dopants in the SiC lattice with minimal damage. Experimental I-V data from Schottky Barrier Diodes (SBDs), combined with TCAD simulation, demonstrated that approximately 40 % of boron atoms were activated in the SiC lattice (at a depth of 30-40 nm) without the need for high temperature ion implant activation. Our approach using plasma treatment realizes an SCR value ρ_c of ~ 5.6×10^-5 Ω∙cm², which is approximately 1 order of magnitude lower than that of untreated samples.

Abstract: A unique hybrid structure of the 4H-SiC bonded substrate offers advantages not achievable with conventional 4H-SiC bulk substrates, such as a reduction in on-state resistance and the suppression of forward bias degradation in power devices. This study focuses on the contact resistance between the polycrystalline layer and the backside metal (Ni/Ti) of 4H-SiC bonded substrates, along with its temperature dependence. The results indicate that the bonded substrates exhibit low backside specific contact resistance (SCR) , even without annealing, and this resistance remains stable at elevated temperatures. Furthermore, power devices utilizing bonded substrates demonstrated reduced on-state resistance, as evaluated using Schottky barrier diodes (SBDs). Specifically, 4H-SiC bonded substrates without contact annealing lowered the forward voltage by 13.4% at room temperature (RT) compared to 4H-SiC bulk substrates with contact annealing. These findings suggest that 4H-SiC bonded substrates simplify the backside contact process compared to 4H-SiC bulk substrates, offering significant benefits in reducing on-state resistance in SiC power devices.