Preface
Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation
p.1
p.1
Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction
p.9
p.9
Impact of Interfacial SiO2 Layer Thickness on the Electrical Performance of SiO2/High-K Stacks on 4H-SiC
p.17
p.17
Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature
p.27
p.27
Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation
p.33
p.33
The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement
p.41
p.41
A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model
p.47
p.47
BCl3 Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC
p.53
p.53
Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction
Abstract:
The impact of silicon nitride (Si₃N₄) stress on 4H-SiC has been investigated. Current-voltage (I-V) measurements on Schottky barrier diode show that Si₃N₄ films thicker than 100 nm degrade both the ideality factor and Schottky barrier height. A 45-nm sacrificial oxidation effectively reduces defects from a 100-nm-thick Si₃N₄ layer, but defects persist with films over 300 nm. Interface state density of metal oxide semiconductor capacitor with a 44-nm-thick gate oxide confirms the effectiveness of sacrificial oxidation in mitigating defects.
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Periodical:
Materials Science Forum (Volume 1158)
Pages:
9-15
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Online since:
September 2025
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