Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Yi Jie Lin; Chuan Han Chen; Ming Han Wang; Bing Yue Tsui

doi:10.4028/p-atG6aA

Paper Titles

Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation
p.1

Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction
p.9

Impact of Interfacial SiO₂ Layer Thickness on the Electrical Performance of SiO₂/High-K Stacks on 4H-SiC
p.17

Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature
p.27

Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation
p.33

The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement
p.41

A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model
p.47

BCl₃ Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC
p.53

HomeMaterials Science ForumMaterials Science Forum Vol. 1158Isolation Structure for Monolithic Integration of...

Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Abstract:

In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and 1700-V VDMOSFET devices on a single 4H-SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reach-through in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV, was then conducted to verify the breakdown voltage (V_BD) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (V_BD) exceeding 2000 V.

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Periodical:

Materials Science Forum (Volume 1158)

Pages:

1-8

DOI:

https://doi.org/10.4028/p-atG6aA

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Online since:

September 2025

Authors:

Yi Jie Lin, Chuan Han Chen, Ming Han Wang, Bing Yue Tsui*

Keywords:

4H-SiC, CMOS, Edge Termination Structure, Monolithic Integration, P-Type Isolation Structure, Silicon Carbide, VDMOSFET

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* - Corresponding Author

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