Materials Science Forum Vol. 1191

Abstract: A body diode is commonly employed as a free-wheeling diode to reduce costs of SiC components instead of an external Schottky barrier diode. However, one of the key issues is higher reverse recovery loss due to bipolar charge contribution to reverse recovery charge. In this study, we investigated the impact of high-temperature annealing on the characteristics of MOSFETs as a cost-effective approach to introduce minority carrier lifetime killers. The trap densities of Z_1/2 center and EH_6/7 center can be controlled by activation annealing temperature. Q_rr of 1900°C measured at 150°C was significantly decrease by 67% compared to that of 1750°C attributed to the 89% suppression of Q_BIP. However, reverse leakage current increased adversely with the activation annealing temperature. R_on and V_th increased with the activation annealing temperature. The trade-off of the annealing temperature worsened slightly compared to that of the doping concentration. It is still possible that high-temperature annealing represents a cost-effective approach to improve the reverse recovery characteristics of the body diode.

Abstract: This study presents the design, fabrication, and electrical characterization of 4H-SiC PIN diodes employed to provide a high electric field able to induce Stark effect in ⁷Be atoms implanted in the space charge region. Indeed, a variation in the half-life of the ⁷Be radioactive decay is expected to be achieved by applying an electric field of the order of 10⁶ V/cm, which can be produced by reverse-biasing 4H-SiC diodes close to the breakdown voltage. A set of diodes of area ranging between 2.12×10^-3 cm² and 9.88×10³ cm² was designed and fabricated to reach breakdown voltages up to 1000 V. When tested under reverse current limitation set equal to 300 nA, over 50% out of 24 devices could withstand reverse bias exceeding 800 V. This work reports on the characteristics of one diode of 9.88×10³ cm² area, implanted with ⁷Be and subject to continuous reverse-bias at 750 V for 107 days. Electrical characterization conducted before, during, and after long-term polarization highlighted an increase in the reverse current generation due to implantation-related defects, which however does not affect the breakdown voltage. These considerations lead to the conclusion that the electric field acting on the implanted ⁷Be remains stable over time, confirming the suitability of 4H-SiC diodes for both induction and measurement of ⁷Be lifetime variations.

Abstract: This work reports enhanced high-voltage blocking capability and an enlarged process window for junction termination extension (JTE) in SiC power devices using a hybrid random and channeling implantation for p-type doping (Al), compared with conventional random-only implantation. A three-step hybrid implantation process has been developed to replace a nine-step random implantation, achieving a similar doping profile and equivalent breakdown voltage in the JTE while significantly increasing fabrication productivity and reducing cost. Moreover, TCAD studies reveal that when using the same number of steps and ion energies as the conventional random implantation method, the JTE realized by the channeling-incorporated hybrid approach enables an increased breakdown voltage and a widened dose window in SiC devices. This is attributed to a deeper Al distribution with a lower average concentration, which effectively alleviates electric field crowding.

Abstract: The heavily doped N+ source region in 4H-SiC MOSFETs is a critical design parameter, as its depth and the profile strongly influence contact resistivity and conduction efficiency. This work investigates the impact of varying N+ implantation depth on the electrical performances of 1.2 kV MOSFETs in both Nominal (linear cell) and Hexagonal (HEXFET) architectures. By varying implantation energy at a fixed dose, three junction depths were obtained: 0.22 µm (shallow), 0.24 µm (moderate), and 0.27 µm (deep). Transfer Length Method (TLM) measurements revealed a significant reduction in source contact resistivity with increasing depth, from 3.91×10⁻⁵ Ω·cm² (shallow) to 1.22×10⁻⁶ Ω·cm² (deep). For Nominal MOSFET design, electrical measurements confirmed a corresponding decrease in specific on-resistance (R_on,sp), from 3.05 to 2.89 mΩ·cm². However, deeper implants introduced greater lateral straggle, shortening the effective channel length and reducing the threshold voltage (V_th) from 2.25 V to 1.96 V. The channel barrier potential lowering associated with lateral straggle increased leakage current in the blocking mode, resulting in reduced breakdown voltage (BV). For Nominal MOSFETs, BV decreased from 1610 V in the shallow split to 1470 V in the deep split, while HEXFETs exhibited sharper BV degradation due to their higher channel density. To address this limitation, optimized JFET doping was introduced, restoring the BV of the deep split to 1560 V in the Nominal architecture. These results demonstrate that although increased N+ depth improves conduction by lowering contact resistance, careful co-optimization with P-well and JFET design is necessary to suppress high leakage current during blocking mode.