Materials Science Forum Vol. 1192

Abstract: This paper presents process integration of atomic layer deposition (ALD) SiO₂ as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance (R_on,sp). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO₂ gate oxide into trench UMOSFET. The R_on,sp of the fabricated device can be reduced to 2.3mΩ-cm², accompanied by a very low density of interface states (D_it) of approximately 5.36x10¹⁰ eV^-1cm^-2. Another feature of this ALD SiO₂ solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

Abstract: This study investigates the electric dipole effect at Al₂O₃/SiO₂ interfaces deposited by Atomic Layer Deposition (ALD) on 4H-silicon carbide (SiC) substrates for threshold voltage (V_T) modulation. By incorporating an ultrathin 3nm Al₂O₃ layer onto ALD-deposited 30nm SiO₂, they created an electric dipole that produces a 0.65±0.15V positive shift in threshold voltage after N₂O post-deposition annealing. The dipole-induced voltage shift was validated through both MOS capacitor measurements and lateral MOSFET characterization. Importantly, the threshold voltage enhancement occurred without degradation in field-effect mobility, demonstrating that the dipole effect does not introduce additional scattering centers. This technique offers an effective approach for threshold voltage tuning in alternative semiconductor devices where thermal SiO₂ growth is not feasible, addressing critical challenges in SiC power electronics that require high threshold voltages (>3V) for reliable operation.

Abstract: This work investigates the impact of different gate oxide fabrication schemes on the electrical characteristics of 4H-SiC planar MOSFETs. Three processes were implemented: (1) 50 nm thermal oxidation with NO annealing at 1350°C, (2) 50 nm ALD-grown oxide with NO annealing at 1250°C, and (3) a stacked 20 nm thermal/30 nm ALD oxide structure with NO annealing at 1250°C. Electrical characterization included I_dV_g, CV, and I_gE_ox measurements. Results show that Condition 1 exhibits the lowest leakage and best uniformity, and demonstrates strong oxide integrity without soft breakdown events. In contrast, Condition 2 and 3 show increased leakage, higher variability, and evidence of soft breakdown, suggesting greater interfacial weakness. However, a surprising trend was observed in the CV analysis: Condition 2’s flat band voltage (VFB​) is closest to the ideal 0V, indicating a lower fixed charge density than Condition 1 [1], which has the most negative VFB​ (≈ -2V). The hysteresis results further highlight differences, with Condition 3 showing the largest hysteresis window (ΔVth​=0.13V). These findings suggest that while the ALD process coupled with a lower-temperature NO anneal (Condition 2) can effectively reduce fixed charges, it does not fully eliminate interfacial defects responsible for increased leakage and soft breakdown. Our results underscore the complex trade-offs in different fabrication schemes, emphasizing that careful interface engineering beyond conventional NO annealing is required to ensure reliable performance in SiC MOSFETs.

Abstract: The increased demand for SiC power MOSFETs requires gate dielectrics with low defect densities and high reliability under high electric field and temperature conditions. In this work, we examine how oxidant chemistry and deposition temperature affect the electrical properties of Al₂O₃/SiO₂ bilayer dielectrics formed in n-type 4H-SiC MOS capacitors. These structures consist of a thin SiO₂ interfacial layer, over which Al₂O₃ is deposited via ALD using three different oxidants at a temperature of 150–350°C. C–V and temperature-dependent I–V (25–150°C) measurements show that the choice of oxidant influences the flat band voltage shift and leakage current density, with a process-dependent trade-off between optimizing each parameter. These findings highlight that precise control of oxidant chemistry during ALD is essential for balancing flat band voltage stability with leakage suppression, and that multilayer-specific conduction models are critical for accurately predicting high electric field leakage characteristics in advanced SiC gate stacks.

Abstract: This work proposes a linear, area‑based component separation method to extract an effective trench sidewall capacitance from C-V measurements of 4H‑SiC UMOS capacitors. Devices were fabricated with two gate‑oxide schemes LPCVD TEOS and low‑temperature oxidation of LPCVD polysilicon and characterized by I-V and C-V measurements. Planar capacitors show breakdown strength above 9 MV/cm. Least‑squares decomposition of layout‑dependent capacitances enabled the separation of mesa, sidewall and bottom contributions. Additionally, this applying this approach revealed trench-pitch dependent depletion and larger wafer‑level thickness variation for the polysilicon‑oxidation flow. Reconstruction errors up to 20 % indicate that spacing‑dependent depletion, corner curvature, fringe and field‑oxide capacitances exceed the simple parallel‑capacitor model.

Abstract: 3C-SiC with a moderate band gap and a large electron affinity is expected to have superior long-term stability against performance degradation. We have fabricated Al-gate MOS diodes in 3C-on-4H-SiC and 4H-SiC regions on a simultaneous lateral epitaxy (SLE) wafer. Here, evaluation results of their high-frequency differential capacitance-voltage (C-V) characteristics are reported and, from suggested band diagrams, carrier transport involved in the phenomena are considered. In the case of n^--type 3C-on-4H-SiC MOS diode, increase in capacitance due to fast modulation in the inversion layer charge (hole) concentration can be confirmed in the negative bias below-5 V. 2-dimensional hole gas (2DHG) is considered at the Si-face 3C/4H heterointerface negatively charged by spontaneous polarization and is expected to be an effective supply source of holes. Especially in the case of p-type 3C-on-4H-SiC MOS diode, it is considered that injection of holes from neutral p-type region into the heterointerface induces compensation of the fixed charges and lowering of the electron barrier at conduction band, and then, electron injection through the barrier causes the fast response of inversion-layer modulation. Appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as “a deep acceptor level” and “2DHG confined by fixed charges”. These findings are believed to contribute to building new production platforms of high-performance power semiconductor devices utilizing the polytype heterostructure of SiC.

Abstract: In this work, we demonstrate a novel oxidation-free gate oxide process consisting of a two-step surface preparation treatment, followed by atomic layer deposition of SiO₂ and a post-deposition anneal in nitrogen. The surface treatment includes a 1300°C anneal in hydrogen and dilute silane, followed by decoupled plasma nitridation (DPN). Long channel MOSFETs fabricated with this process show a 1.5X improvement in peak field effect mobility compared with devices utilizing a standard thermal oxide and NO anneal. The MOSFETs had a positive threshold voltage, low gate leakage, and a breakdown field of nearly 10 MV/cm.

Abstract: In this work, we present a process flow to optimize the SiC/SiO₂ gate interface quality for SiC power MOSFETs. The process incorporates high-temperature N₂/H₂ pretreatment, followed by LPCVD SiO₂ deposition and NO post-deposition annealing (PDA). By tailoring the pretreatment conditions, a substantially improved SiC/SiO₂ interface with reduced interface trap density (D_it) can be achieved. Furthermore, the gate oxide quality is also characterized by measuring the leakage current and time-dependent dielectric breakdown (TDDB). The results indicate a noticeable improvement in the average breakdown field (E_ox), thanks to the enhanced SiC surface condition achieved by the N₂/H₂ pretreatment.

Abstract: We investigate the physical and electrical characteristics of the Al-doped or undoped HfO₂/SiO₂ gate stacks on 4H-SiC by testing MOSCAP chips fabricated in house. A clear reduction in accumulation capacitance (C_ox) with increasing chuck temperature from room temperature up to 523 K is observed, with Al-doping playing a key role and aligning with temperature-dependent Landau ferroelectric theory. Chips annealed at 1100°C in N₂ ambient show the highest C_ox decrease rates while maintaining functional MOS interfaces with acceptable flatband voltage, hysteresis, and Dit profiles. TCAD simulations on a double trench MOSFET model, based on the extracted data indicate improved electro-thermal performance, demonstrating that Al-doped HfO₂/SiO₂ gate stacks are a promising approach for enhancing 4H-SiC power devices.