Demonstration of ALD SiO₂ as Gate Oxide in the 1.7kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Abstract:

This paper presents process integration of atomic layer deposition (ALD) SiO₂ as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance (R_on,sp). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO₂ gate oxide into trench UMOSFET. The R_on,sp of the fabricated device can be reduced to 2.3mΩ-cm², accompanied by a very low density of interface states (D_it) of approximately 5.36x10¹⁰ eV^-1cm^-2. Another feature of this ALD SiO₂ solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

• Periodical: Materials Science Forum (Volume 1192)
• Pages: 1-7
• DOI: https://doi.org/10.4028/p-BBnM7g
• Online since: May 2026
• Authors: Chia Lung Hung*, Patrick Rabinzohn, Andrii Vozny, Tatiana Ivanova, Mikko Söderlund, Yi Kai Hsiao, Hao Chung Kuo
• Keywords: 4H-SiC, Atomic Layer Deposition (ALD), Density of Interface States, Embedded CMOS, SiO₂, Specific On-State Resistance, Trench UMOSFET

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