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Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes
Abstract:
This work investigates the impact of different gate oxide fabrication schemes on the electrical characteristics of 4H-SiC planar MOSFETs. Three processes were implemented: (1) 50 nm thermal oxidation with NO annealing at 1350°C, (2) 50 nm ALD-grown oxide with NO annealing at 1250°C, and (3) a stacked 20 nm thermal/30 nm ALD oxide structure with NO annealing at 1250°C. Electrical characterization included IdVg, CV, and IgEox measurements. Results show that Condition 1 exhibits the lowest leakage and best uniformity, and demonstrates strong oxide integrity without soft breakdown events. In contrast, Condition 2 and 3 show increased leakage, higher variability, and evidence of soft breakdown, suggesting greater interfacial weakness. However, a surprising trend was observed in the CV analysis: Condition 2’s flat band voltage (VFB) is closest to the ideal 0V, indicating a lower fixed charge density than Condition 1 [1], which has the most negative VFB (≈ -2V). The hysteresis results further highlight differences, with Condition 3 showing the largest hysteresis window (ΔVth=0.13V). These findings suggest that while the ALD process coupled with a lower-temperature NO anneal (Condition 2) can effectively reduce fixed charges, it does not fully eliminate interfacial defects responsible for increased leakage and soft breakdown. Our results underscore the complex trade-offs in different fabrication schemes, emphasizing that careful interface engineering beyond conventional NO annealing is required to ensure reliable performance in SiC MOSFETs.
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15-20
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Online since:
May 2026
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