Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al₂O₃/SiO₂ Interface Dipole Engineering

Bongmook Lee; Veena Misra

doi:10.4028/p-rMav12

Paper Titles

Demonstration of ALD SiO₂ as Gate Oxide in the 1.7kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration
p.1

Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al₂O₃/SiO₂ Interface Dipole Engineering
p.9

Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes
p.15

Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al₂O₃/SiO₂/SiC MOS-Capacitors
p.21

Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation
p.29

Characterization of Al-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method
p.39

Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition
p.47

Characterizations of 4H-SiC/SiO₂ Interface by High-Temperature N₂/H₂ Pretreatment
p.53

HomeMaterials Science ForumMaterials Science Forum Vol. 1192Threshold Voltage Control in 4H-SiC MOS Devices by...

Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al₂O₃/SiO₂ Interface Dipole Engineering

View Pdf By email

Abstract:

This study investigates the electric dipole effect at Al₂O₃/SiO₂ interfaces deposited by Atomic Layer Deposition (ALD) on 4H-silicon carbide (SiC) substrates for threshold voltage (V_T) modulation. By incorporating an ultrathin 3nm Al₂O₃ layer onto ALD-deposited 30nm SiO₂, they created an electric dipole that produces a 0.65±0.15V positive shift in threshold voltage after N₂O post-deposition annealing. The dipole-induced voltage shift was validated through both MOS capacitor measurements and lateral MOSFET characterization. Importantly, the threshold voltage enhancement occurred without degradation in field-effect mobility, demonstrating that the dipole effect does not introduce additional scattering centers. This technique offers an effective approach for threshold voltage tuning in alternative semiconductor devices where thermal SiO₂ growth is not feasible, addressing critical challenges in SiC power electronics that require high threshold voltages (>3V) for reliable operation.

You have full access to the following eBook

Interface, Dielectrics and Ohmic Contact in SiC Power Devices

Read eBook

Info:

Periodical:

Materials Science Forum (Volume 1192)

Pages:

9-13

DOI:

https://doi.org/10.4028/p-rMav12

Citation:

Cite this paper

Online since:

May 2026

Authors:

Bongmook Lee*, Veena Misra

Keywords:

4H-SiC Power Device, Atomic Layer Deposition (ALD), Dipole Effect, V_FB Modulation, V_T Modulation

Export:

RIS, BibTeX

Permissions:

Creative Commons CC BY 4.0

Citation:

* - Corresponding Author

References

[1] T. -H Kil, M. Noguchi, H. Watanabe, and K. Kita, "Impact of Al2O3/SiO2 interface dipole layer formation on the electrical characteristics of 4H-SiC MOSFET," IEEE Electron Device Letters, 43 (1), 2022.

DOI: 10.1109/led.2021.3125945

Google Scholar

[2] P. D. Kirsch et al, "Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning," Appl. Phys. Lett., vol. 92, no. 9, pp.092-901, Mar. 2008.

DOI: 10.1149/ma2009-01/15/725

Google Scholar

[3] K. Kita and A. Toriumi, "Origin of electric dipoles formed at high-k/SiO2 interface," Appl. Phy. Lett., vol. 94, no. 13, pp.132-902, April. 2009.

DOI: 10.1063/1.3110968

Google Scholar

[4] B. Lee, S. Novak, D. Lichtenwalner, X. Yang, and V. Misra, "Investigation of the origin of VT/VFB modulation by La2O3 capping layer approaches for NMOS application: Role of La diffusion, Effect of host high-k layer, and interface properties," IEEE Transactions on Electron Devices, Vol. 58, no. 9, pp.3106-3115, 2011.

DOI: 10.1109/ted.2011.2159306

Google Scholar

[5] S. M. George, "Atomic layer deposition: An overview," Chem. Rev., vol. 110, no. 1, p.111–131, Jan. 2010.

Google Scholar

[6] R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, "A capacitance-based methodology for work function extraction of metals on high-κ," IEEE Electron Device Lett., vol. 25, pp.420-2004.

DOI: 10.1109/led.2004.829032

Google Scholar

[7] J. R. Hauser and K. Ahmed, "Characterization of ultra-thin oxides using electrical C–V and I–V measurements," in Proc. AIP Conf., 1998, p.235–239.

DOI: 10.1063/1.56801

Google Scholar

[8] X. Yang, B. Lee, and V. Misra, "Electrical characteristics of SiO2 deposited by Atomic Layer Deposition on 4H-SiC after nitrous oxide anneal," IEEE Transactions on Electron Devices, vol. 63, no. 7, pp.2826-2830, 2016.

DOI: 10.1109/ted.2016.2565665

Google Scholar