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Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes
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Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors
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Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation
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Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

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Abstract:

This work proposes a linear, area‑based component separation method to extract an effective trench sidewall capacitance from C-V measurements of 4H‑SiC UMOS capacitors. Devices were fabricated with two gate‑oxide schemes LPCVD TEOS and low‑temperature oxidation of LPCVD polysilicon and characterized by I-V and C-V measurements. Planar capacitors show breakdown strength above 9 MV/cm. Least‑squares decomposition of layout‑dependent capacitances enabled the separation of mesa, sidewall and bottom contributions. Additionally, this applying this approach revealed trench-pitch dependent depletion and larger wafer‑level thickness variation for the polysilicon‑oxidation flow. Reconstruction errors up to 20 % indicate that spacing‑dependent depletion, corner curvature, fringe and field‑oxide capacitances exceed the simple parallel‑capacitor model.

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Periodical:

Materials Science Forum (Volume 1192)

Pages:

29-37

DOI:

https://doi.org/10.4028/p-C8ENIb

Citation:

Cite this paper

Online since:

May 2026

Authors:

Maximilian Szabo*, Tom Becker, Michael Jank, Tobias Erlbacher

Keywords:

4H-SiC, Capacitors, Linear Component Separation, Metal-Oxide-Semiconductor (MOS), Trench, Trench Sidewall Capacitance

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Creative Commons CC BY 4.0

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