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Characterizations of 4H-SiC/SiO2 Interface by High-Temperature N2/H2 Pretreatment

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Abstract:

In this work, we present a process flow to optimize the SiC/SiO2 gate interface quality for SiC power MOSFETs. The process incorporates high-temperature N2/H2 pretreatment, followed by LPCVD SiO2 deposition and NO post-deposition annealing (PDA). By tailoring the pretreatment conditions, a substantially improved SiC/SiO2 interface with reduced interface trap density (Dit) can be achieved. Furthermore, the gate oxide quality is also characterized by measuring the leakage current and time-dependent dielectric breakdown (TDDB). The results indicate a noticeable improvement in the average breakdown field (Eox), thanks to the enhanced SiC surface condition achieved by the N2/H2 pretreatment.

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Periodical:

Materials Science Forum (Volume 1192)

Pages:

53-57

DOI:

https://doi.org/10.4028/p-2GRnYr

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Cite this paper

Online since:

May 2026

Authors:

Heng Wang*, Yang Ming Du, Ji Shu, Peng Wei Zhou, Ying Chen Yang, Kevin J. Chen

Keywords:

4H-SiC MOS Capacitor, Gate Leakage Current, High Temperature Pretreatment, Interface Trap Density, SiC/SiO2 Interface

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References

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