Materials Science Forum Vol. 1191

Abstract: In this paper, the radiation resistance of GaN and SiC is compared. The effect of the irradiation temperature on the carrier removal rate in both semiconductors during proton irradiation is considered. It was found that in GaN, as well as in SiC, the rate of carrier removal decreases with increasing irradiation temperature. The dependence of the GaN sample resistance on the radiation dose was also calculated based on a model previously proposed to describe a similar dependence for SiC. Based on the experimental data obtained, it is concluded that the processes of radiation compensation in GaN and SiC are similar.

Abstract: Controlling wafer warpage is critical for SiC power device fabrication on 200 mm substrates. Residual mechanical stress in bare SiC wafers is a major contributor to bow and warp. In this study, photoelastic measurements were employed to reveal distinct stress levels among wafers from different vendors, which reflect differences in crystal growth and wafering processes. By decomposing the stress into radial and tangential components, two dominant stress distribution modes—symmetric and asymmetric—were identified. The results demonstrate a clear correlation between residual mechanical stress and wafer warpage in 200 mm SiC substrates.

Abstract: The measurement of thin silicon dioxide (SiO₂) layers on silicon carbide (SiC) substrates is crucial because these layers serve a variety of critical functions in electronic and optoelectronic devices. Silicon carbide’s superior electrical and thermal properties make it a preferred material for high-power, high-frequency, and high-temperature applications. When deposited on SiC, thin SiO₂ films act as preconditioning layers, and as gate oxides, precise measurement of these oxide layers is important to ensure both optimal functionality and extended device longevity. This paper presents the essential considerations that should be addressed when Silicon-Oxide layers on SiC substrate are measured by spectroscopic ellipsometry to avoid backside artifact and enhance sensitivity in their thickness measurements. The methodology demonstrated enables reliable detection of layer thicknesses down to less than 1 nm, with a discrimination of less than ±0.5 nm. During ellipsometry data evaluation, parametric models are applied to describe the anisotropic backside reflections. Incorporating additional parameters, such as the substrate thickness, can yield deeper insights into the sample. However, this added complexity can render the modeling approach impractical for routine industrial applications, even though it remains scientifically valuable. Overall, this study emphasizes the combined importance of using a microspot system and optimizing the incidence angle to overcome the inherent challenges of measuring thin SiO₂ films on 4H-SiC.

Abstract: We present a new method to potentially map the effective minority charge carrier lifetime by means of a chopped electron beam induced current in a scanning electron microscope using a digital lock-in amplifier. While previous authors have been mainly interested in measuring the diffusion length and some even the minority charge carrier lifetime using line-scans, we show that this method could be extended to measure the lifetime locally in the cross section of a given device. In our case, we use a simple SiC pn-junction. The decrease of current with increasing chopping frequency of the electron beam makes a direct measurement of the effective lifetime possible. Inspired by optical beam induced current (OBIC), this novel approach has great potential to measure the minority charge carrier lifetime locally and is going to help device and process engineers to develop the next generation of SiC power devices.

Abstract: An area of increasing interest for SiC device processing is the processing and qualification of silicon oxides. In this article a contactless corona CV (CnCV) measurement procedure is evaluated as a way to gain more knowledge about the different processes related to oxides. A 21-point measurement pattern is used to gain information about uniformity of oxide properties. Two different types of oxides have been considered, low pressure chemical vapor deposited (CVD) oxides using tetraethylorthosilicate (TEOS) and thermally grown oxides. The two different groups have received different combinations of pre- and post-processing steps prior to measurements. As expected, low pressure CVD (LPCVD) and thermally grown SiO₂ without any post oxidation annealing (POA) showed significantly different electrical characteristics compared to the wafers that did get a POA. This difference could clearly be distinguished by CnCV, meaning that individual process steps can be analyzed without the fabrication of any test structures on the wafers. As the individual process steps can be analyzed, the uniformity of the individual steps can be accessed. Using a 21-point pattern it was possible to show that there is a non-uniformity in the LPCVD process used prior to the POA. This makes the CnCV technique suitable for in-line characterization and process monitoring.

Abstract: Silicon carbide (SiC) is a wide-bandgap semiconductor that has attracted considerable attention for the development of advanced electronic and sensing devices. Thanks to its combination of high breakdown field, excellent thermal conductivity, and chemical stability, SiC enables operation in conditions where conventional semiconductors fail. In this study, the Optical Beam Induced Current (OBIC) technique will be employed to analyze the electric field distribution within the structure of SiC bipolar diodes featuring varying epitaxial layer thicknesses. To create OBIC signal we have used ultraviolet laser beam. We have tested bipolar diodes with both 10 µm and 100 µm epilayer thicknesses. We have obtained several OBIC signals by re-scanning the same location at different reverse voltages applied to the same SiC diode. Also, Synopsis TCAD simulations of the electric field are reported for both diodes. In these simulations it is possible to observe the increase of the electric field at the edge of the devices that are observed by the OBIC measurements. In conclusion, OBIC technique aids in optimizing device design and improving overall performance.

Abstract: The impact on doping profile, surface roughness and defect production of each process step for a suggested Multiple epitaxy and implantation (MEI) process for Super-junction has been investigated through Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. Results show that the suggested process can possibly reduce the cost of the original fabrication and speed up the process.

Abstract: The effects of 673K temperature anneal on a 4H-SiC CMOS NOT logic gate have been investigated. After an annealing at 673K for 30 minutes in ambient atmosphere, a shift of threshold logic voltage, V_M, towards higher input voltage by 6.67%, and a hysteresis reduction are observed. Both effects can be related to MOSFETs electrical behavior after the same thermal annealing. The threshold voltage of NMOSFET, V_{TH, N}, increases by 6.67%, whereas PMOSFET one reduces by 11.15%, allowing the V_M increase. NMOSFET shows a reduction of its trans-characteristic hysteresis, ΔV_H, by-33.3%, as well as PMOSFET one, that is by-20.4%, explaining the hysteresis reduction of NOT gate. Moreover, a more reproducible NOT transfer characteristics is obtained after the 673K annealing.

Abstract: Achieving reliable breakdown in ultra-high-voltage (>10 kV) SiC devices is limited by edge termination design, where low epitaxial doping (~4×10¹⁴ cm⁻³) results in lateral straggle to be more prominent, therefore necessitating wider spacing between Aluminum implants in conventional floating field rings (FFRs). This study introduces a background doping modulation (BDM) scheme, incorporating a moderately doped N-type confinement region within P+ rings, enabling tighter spacing without added process complexity for high-voltage MOSFETs. Fabricated BDM-FFRs achieved >13 kV breakdown (30% higher than conventional FFRs), with leakage current <10 nA at 10 kV, while reducing termination area by 18.6%. Therefore, the BDM-FFR demonstrates a scalable, compact, and high-performance edge termination approach for next-generation ultra-high-voltage SiC devices.