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HomeMaterials Science ForumMaterials Science Forum Vol. 1191Effects of 673K Temperature Anneal on a 4H-SiC...

Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

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The effects of 673K temperature anneal on a 4H-SiC CMOS NOT logic gate have been investigated. After an annealing at 673K for 30 minutes in ambient atmosphere, a shift of threshold logic voltage, V_M, towards higher input voltage by 6.67%, and a hysteresis reduction are observed. Both effects can be related to MOSFETs electrical behavior after the same thermal annealing. The threshold voltage of NMOSFET, V_{TH, N}, increases by 6.67%, whereas PMOSFET one reduces by 11.15%, allowing the V_M increase. NMOSFET shows a reduction of its trans-characteristic hysteresis, ΔV_H, by-33.3%, as well as PMOSFET one, that is by-20.4%, explaining the hysteresis reduction of NOT gate. Moreover, a more reproducible NOT transfer characteristics is obtained after the 673K annealing.

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Materials Science Forum (Volume 1191)

Pages:

49-53

DOI:

https://doi.org/10.4028/p-4zjeaP

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Online since:

May 2026

Authors:

Nicola Rinaldi*, Luigi di Benedetto, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Keywords:

4H-SiC CMOS Technology, 4H-SiC Lateral MOSFETs, 673K Annealing, NOT Logic Gate

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