Bias-Temperature-Stress Response of Commercially-Available SiC Power MOSFETs

Ronald Green; Aivars J. Lelis; Mooro El; Daniel B. Habersat

doi:10.4028/www.scientific.net/MSF.821-823.677

Paper Titles

Robust Double-Ring Junction Termination Extension Design for High Voltage Power Semiconductor Devices Based on 4H-SiC
p.656

Industrial Approach for Next Generation of Power Devices Based on 4H-SiC
p.660

Proton and Electron Irradiation in Oxynitrided Gate 4H-SiC MOSFET: A Recent Open Issue
p.667

Instability of Critical Electric Field in Gate Oxide Film of Heavy Ion Irradiated SiC MOSFETs
p.673

Bias-Temperature-Stress Response of Commercially-Available SiC Power MOSFETs
p.677

Degradation and Reliability of Bare Dies Operated up to 300°C
p.681

Exact Characterization of Threshold Voltage Instability in 4H-SiC MOSFETs by Non-Relaxation Method
p.685

SiC MOSFETs in Hard-Switching Bidirectional DC/DC Converters
p.689

Channel Mobility Improvement in 4H-SiC MOSFETs Using a Combination of Surface Counter-Doping and NO Annealing
p.693

HomeMaterials Science ForumMaterials Science Forum Vols. 821-823Bias-Temperature-Stress Response of...

Bias-Temperature-Stress Response of Commercially-Available SiC Power MOSFETs

Abstract:

The stability of the threshold voltage of commercial SiC MOSFETs from two device manufactures has been evaluated and compared when subject to positive and negative bias-temperature-stress conditions. For both device groupings, the worse-case stress occurred under negative bias temperature conditions with V_GS = –15 V and a stress temperature of 200 °C. Devices in the Vendor A grouping exhibited acceleration in their bias-temperature-stress response that occurred earlier in time as a strong function of stress-temperature and to a lesser degree on gate-bias magnitude. Devices in the Vendor B grouping showed some evidence of acceleration, but only for the worse-case stress condition. Threshold voltage shifts for this device group were very low and extremely stable, with recorded values below 0.4 V for most conditions.

You might also be interested in these eBooks

Silicon Carbide and Related Materials 2014

View Preview

Info:

Periodical:

Materials Science Forum (Volumes 821-823)

Pages:

677-680

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.821-823.677

Citation:

Cite this paper

Online since:

June 2015

Authors:

Ronald Green*, Aivars J. Lelis, Mooro El, Daniel B. Habersat

Keywords:

BTS, Charge Trapping, DMOSFET, VT Instability

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] A.J. Lelis, R. Green, and D. Habersat, Mater. Sci. Forum 679-680, 599 (2011).

Google Scholar

[2] A.J. Lelis, D. Habersat, R. Green, A. Ogunniyi, M. Gurfinkel, J. Suehle, and N. Goldsman, IEEE Trans. Elec. Dev. 55(8), 1835 (2008).

DOI: 10.1109/ted.2008.926672

Google Scholar

[3] A. Lelis, R. Green, M. El, and D. Habersat, Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs, to be published in IEEE Trans. Elec. Dev., (2015).

DOI: 10.1109/ted.2014.2356172

Google Scholar

[4] R. J. Kaplar, et al., Proc. Electrical Energy Storage Applications & Technologies (EESAT) Conference (2011).

Google Scholar

[5] J. Senzaki, A. Shimozato, K. Kojima, S. Harada, K. Ariyoshi, T. Kojima,Y. Tanaka, and H. Okumura, Mater. Sci. Forum 778-780, 521 (2014).

DOI: 10.4028/www.scientific.net/msf.778-780.521

Google Scholar

[6] G. Pobegen, T. Aichinger, A. Salinaro, and T. Grasser, Mater. Sci. Forum 778-780, 959 (2014).

DOI: 10.4028/www.scientific.net/msf.778-780.959

Google Scholar