Materials Science Forum Vols. 821-823

Abstract: This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO₂) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO₂ gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Abstract: We proposed an improved method for evaluating the effective channel mobility (μ_eff), involving an appropriate definition of the threshold voltage (V_th) based on the ideal gate bias voltage – drain current (V_G-I_D) characteristics. Using this method, the dependence of μ_eff on the effective field (E_eff) could be evaluated even for SiC trench MOSFETs with large interface state density (D_it) values. The dominant influence on μ_eff in the low E_eff region was found to be Coulomb scattering caused by interface states at the SiC/SiO₂ interfaces.

Abstract: This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (R_on,sp) and the maximum bottom oxide electric field (E_ox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication, R_on,sp of the trench-gate SiC-MOSFET with DS is70 % lower than that without DS at a trench depth (d_t) of about 1.5 mm. The d_tof the trench-gate SiC-MOSFET with DS can be designed 25 % shallower than thatwithout DS at a R_on,sp of about 3.0 mWcm².Therefore, it can reduce the JFET resistance and allow to shrinkthe trench depth. Optimizing the parametersof DS, the structure having DS is an effective means of reducing the JFETresistance, while reducing E_ox by minimizing the depth of the trench.

Abstract: A new MOSFET structure named the CIMOSFET (Central Implant MOSFET) has been presented and experimentally confirmed on SiC. The novelty of the CIMOSFET lies in a p-type implant introduced in the middle of the JFET area to shield the oxide interface field from the drain bias. Compared to the commercially available 1200 V SiC DMOSFET, this new concept has significantly reduced the on-resistance (R_on) and gate-drain capacitance (C_gd) simultaneously, produced a record low R_on·Q_gd Figure of Merit of 455 mΩ·nC at 25°C, and 700 mΩ·nC at 150°C (~30% of the best data found). Only a 55% increase in R_on from 25°C to 150°C has been achieved due to the highly doped drift layer used on the CIMOSFET. Inductive load switching measurements have shown the CIMOSFET exhibits a fast switching performance. The CIMOSFET blocks 1600 V even though its drift doping is higher than that of the conventional DMOSFETs.

Abstract: 3kV UMOSFET with buried p-base regions was developed to realize the low on-resistance with low electric field in the gate oxide for off-state. The buried p-base region was formed simultaneously with the p-base region by utilizing MeV ion implantation. Influence by the structural parameter such as cell geometry and space between the buried p-base region and the trench gate was investigated. The hexagonal cell with high channel density exhibits an extremely low on-resistance of 6.8 mΩcm² with threshold voltage of 5.0 V at room temperature.

Abstract: The effect of the crystal quality and surface morphology on the electrical properties of MOS capacitors has been studied in devices manufactured on 3C-SiC epitaxial layers grown on Silicon (100) substrate. The interface state density, which represents one of the most important parameters for the 3C-SiC MOSFET development, has been determined through capacitance measurements. A cross-correlation between High Resolution X-ray Diffraction, AFM analysis and electrical conductance measurements has allowed determining the relationship between the crystalline quality and the interface state density. By improving the crystalline quality, a decrease of the interface state density down to 10¹⁰ cm^-2 eV^-1 was observed.

Abstract: The cryogenic performance of two commercially available SiC power MOSFETs are presented in this work. The devices are characterised in static and dynamic tests at 10 K intervals from 20-320 K. Static current-voltage characterisation indicates that at low temperatures threshold voltage, turn-on voltage, on-state resistance, transconductance, and the body diode turn-on voltage all increase while saturation current decreases. Dynamic, 60 V, 3A switching tests within the cryogenic chamber are also reported and the trends of switching speed, losses, and total power losses, which rise at low temperature, are presented. Overall, both MOSFETs are fully operable down to 30 K with both positive and negative changes in behaviour.

Abstract: This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA’s on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 °C. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 °C to 500 °C.

Abstract: Commercial 1200V and 1700V MPS diodes and 1700V vertical JFETs produced on 4H-SiC n-type epilayers were neutron irradiated with fluences up to 4x10¹⁴ cm^-2 (1 MeV neutron equivalent Si). Radiation defects and their effect on carrier removal were investigated by capacitance deep-level transient spectroscopy, I-V and C-V measurement. Results show that neutron irradiation introduces different point defects giving rise to deep acceptor levels which compensate nitrogen doping of the epilayer. The carrier removal rate increases linearly with nitrogen doping. Introduced defects deteriorate ON-state characteristics of irradiated devices while their effect on blocking characteristics is negligible. The effect of neutron irradiation can be simulated by TCAD tools using a simple model accounting for introduction of one dominant deep level (Z1/Z2 centre).

Abstract: Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P⁺ SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P⁺ and ion implanted N⁺ layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P⁺ VLS gate layer, probably due to imperfect VLS (P⁺) / CVD (N⁺) SiC interface.