Electrical Characterization of a 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

Philip G. Neudeck; Liang Yu Chen; David J. Spry; Glenn M. Beheim; Carl W. Chang

doi:10.4028/www.scientific.net/MSF.821-823.781

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HomeMaterials Science ForumMaterials Science Forum Vols. 821-823Electrical Characterization of a 4H-SiC JFET...

Electrical Characterization of a 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

Abstract:

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA’s on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 °C. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 °C to 500 °C.

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Periodical:

Materials Science Forum (Volumes 821-823)

Pages:

781-784

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.821-823.781

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Online since:

June 2015

Authors:

Philip G. Neudeck*, Liang Yu Chen, David J. Spry, Glenn M. Beheim, Carl W. Chang

Keywords:

4H-SiC, High Temperature, I-V, Junction Field Effect Transistor (JFET), Oven Testing, Wafer Mapping

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