VLS Grown 4H-SiC Buried P+ Layers for JFET Lateral Structures

Selsabil Sejil; Farah Laariedh; Mihai Lazar; Davy Carole; Christian Brylinski; Dominique Planson; Gabriel Ferro; Christophe Raynaud; Hervé Morel

doi:10.4028/www.scientific.net/MSF.821-823.789

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HomeMaterials Science ForumMaterials Science Forum Vols. 821-823VLS Grown 4H-SiC Buried P+ Layers for JFET Lateral...

VLS Grown 4H-SiC Buried P⁺ Layers for JFET Lateral Structures

Abstract:

Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P⁺ SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P⁺ and ion implanted N⁺ layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P⁺ VLS gate layer, probably due to imperfect VLS (P⁺) / CVD (N⁺) SiC interface.

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Materials Science Forum (Volumes 821-823)

Pages:

789-792

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.821-823.789

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Online since:

June 2015

Authors:

Selsabil Sejil, Farah Laariedh, Mihai Lazar*, Davy Carole, Christian Brylinski, Dominique Planson, Gabriel Ferro, Christophe Raynaud, Hervé Morel

Keywords:

Junction Field Effect Transistor (JFET), Roughness, TLM, VLS Epitaxial Growth

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