Materials Science Forum Vols. 821-823

Abstract: The electronic packaging has developed in the changing trend from soldering to solderless technology bonding to achieve higher performance of devices. Moreover, power electronic devices have searching for an alternative interconnection technology to replace the high temperature solder with high Pb contents, particularly suitable for next-generation wide band-gap (WBG) semiconductors such as SiC or GaN. In this study, our pressureless Ag thin-film die-attach gives an opportunity to produce the mass production by realizing low-temperature process. We demonstrate the pressureless Ag thin-film die-attach with Si and SiC to explain the mechanisms underlying the bonding process. The variation of the substrate material modifies the thermal expansion mismatch between sputtered Ag film and the substrate, and changes the bonding property, in particular die-shear strength. We reveal that the thermal stress generated by heating plays one of key roles to control the pressureless Ag thin-film die-attach process.

Abstract: Heat-resistance of novel mold compound made of silsesquioxane nanocomposite with silica fillers is demonstrated in a TO247 package of SiC SBD. The test specimens are exposed to thermal cycling between -50°C and 250°C, and the thermal damage of the mold are precisely evaluated by using nanoscale dynamical mechanical analysis based on nanoindentation technology. The results reveal that the excellent heat-resistance is brought by the miscibility between the thermosetting nanocomposite and silica fillers.

Abstract: The electrical properties of the interface between quasi free standing bilayer graphene (QFBLG) and SiC(0001) have been investigated by nanoscale resolution current measurements using conductive atomic force microscopy (CAFM). I-V analyses were carried out on Au-capped QFBLG contacts with different sizes (from 200 down to 0.5 μm) fabricated on SiC samples with different miscut angles (from on-axis to 3.5° off-axis). The extracted QFBLG/SiC Schottky barrier height (SBH) was found to depend on the contact size. SBH values ∼0.9-1 eV were obtained for large contacts, whereas a gradual increase was observed below a critical (micrometer scale) contact size (depending on the SiC miscut angle) up to values approaching ∼1.5 eV. Nanoscale resolution current mapping on bare QFLBG contacts revealed that SiC step edges and facets represent preferential current paths causing the effective SBH lowering for larger contacts. The reduced barrier height in these regions can be explained in terms of a reduced doping of QFBLG from SiC substrate at (11-20) step edges with respect to the p-type doping on the (0001) terraces.

Abstract: Epitaxial graphene on silicon carbide (SiC) can easily be grown by thermal decomposition. A well-defined epitaxial interface between graphene and substrate is formed, especially when the silicon face of hexagonal polytypes is employed. It is found that as-grown monolayer graphene with interfacial buffer layer provides perfectly ohmic contacts to n-type SiC – even to low-doped epitaxial layers without contact implantation. Contact resistances to highly doped samples are competitive with conventional annealed nickel (Ni) contacts; a direct comparison of Ni and graphene contacts on 4H-SiC resulted in an one order of magnitude reduction of the contact resistance in the case of graphene contacts. On highly doped 6H-SiC, a specific contact resistance as low as ρ_C = 5.9·10^-6 Ωcm² was found. This further improvement compared to 4H-SiC is assigned to better matching of work functions at the Schottky-like interface.

Abstract: Top-gated field-effect transistors have been created from bilayer epitaxial graphene samples that were grown on SiC substrates by a vacuum sublimation approach. A high-quality dielectric layer of Al₂O₃ was grown by atomic layer deposition to function as the gate oxide, with an e-beam evaporated seed layer utilized to promote uniform growth of Al₂O₃ over the graphene. Electrical characterization has been performed on these devices, and temperature-dependent measurements yielded a rise in the maximum transconductance and a significant shifting of the Dirac point as the operating temperature of the transistors was increased.

Abstract: Few layers graphene has been grown on 4H-SiC. Since this material has outstanding electronic properties, we aimed fabricating graphene field-effect transistors on silicon carbide wafer. Growth of the graphene layers was made by e-beam sublimation of silicium under ultra high vacuum (UHV). These layers were patterned and used as channels of transistors with source and drain made of P⁺ SiC. The different technological steps were checked through Raman spectroscopy, Scanning Electron Microscopy (SEM), and electrical characterizations.

Abstract: The technique of reflection high-energy electron diffraction (RHEED) has been applied to study the graphene growth on conductive and semi-insulating 6H-SiC (0001) substrates using two RHEED devices. It was found the oriented growth of graphene on the conductive wafer and both oriented as disordered graphene growth on semi-insulating wafer due to the partial formation of polycrystalline component in nanocarbon film. It was shown that the appearance of the graphene polycrystalline phase was caused by the lower perfection structure of the surface of the semi-insulating substrate as compared to the conductive substrate.

Abstract: Effects of residual oxygen in an annealing chamber on graphitization of SiC along with surface pre-treatment process have been investigated. As a pre-treatment process, SiO₂ was formed on 4H-SiC(0001) substrates by thermal oxidation before graphene formation annealing. Epitaxial graphenes were formed in several O₂ pressures and effects on graphitization of SiC were evaluated. It is shown that quality of graphene on SiC substrates which formed without pre-oxidation degraded by the presence of residual O₂ in the chamber. It is demonstrated that SiO₂ pre-oxidation films (about 10nm) were effective to prevent such degradations, for all O₂ pressures that we examined in this work. In addition, at O₂ pressure of 1.1x10^-1Pa, with SiO₂ pre-oxidation, a graphene growth rate was increased, which indicates that a certain level of O₂ pressure enhances graphene growth.

Abstract: Graphene is a 2D material with potential for almost any purpose, thanks to a combination of excellent characteristics, e.g. high electrical conductivity. Graphene grown on SiC wafers is one of the promising routes for graphene integration into planar technology electronic applications. Synthesis is based on the decomposition of a SiC single crystal surface at high temperature, where Si-terminated SiC substrates require the formation of the C buffer layer. In spite of numerous experimental and theoretical works the understanding and control upon crucial factors such as step and terrace stability or surface roughening is far from been fully comprehended and then technologically optimized. We present experimental results on the deposition of graphene onto Si-terminated 6H-SiC. We analyze the effect of ex situ and in situ conditionings of the SiC surface in the thermal decomposition and reconstruction of the SiC terraces, toward higher control upon the growth process of graphene films.

Abstract: Large-area epitaxial graphene formed on C-face SiC has been investigated by Raman Spectroscopy and SEM (scanning electron microscopy). Local Raman spectra showed a large homogeneous area of high quality epitaxial FLG (few layer graphene) has been fabricated on C-face SiC. Our work reveals unexpectedly the shift in Raman peak position across the samples resulting from the inhomogeneity in the strains and impurities of the graphene films, which we exhibit to be correlated with physical topography by combining Raman spectroscopy with scanning electron microscopy (SEM)