Development of Integrated Wet Cleans for 3D-SIC Technologies

Article Preview

Abstract:

3D stacked IC (3D-SIC) is one of the main approaches within 3D technologies as it is the most mature and economically viable technology and provides the highest through silicon via density. Enabling 3D SIC requires the modification of standard IC process flows by adding several process modules, such as through silicon via (TSV), wafer bonding and thinning, prior backside processing (e.g. Cu nails exposure), micro bumps formation for the front side and/or the backside and finally stacking to another chips [. Within the 3D-SIC technology developed at IMEC, surface control and preparation by means of wet clean and wet etch are essential steps notably in two key process modules: wafer thinning and micro bump formation.

You might also be interested in these eBooks

Info:

Periodical:

Solid State Phenomena (Volume 195)

Pages:

150-153

Citation:

Online since:

December 2012

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2013 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] A. Jourdain, T. Buisson, A. Phommahaxay, A. Redolfi, S. Thangaraju, Y. Travaly, E. Beyne, B. Swinnen, IEEE 61st Electronic Components and Technology Conference, pp.1122-1125, (2011).

DOI: 10.1109/ectc.2011.5898650

Google Scholar

[2] K. Wostyn et al., 10th International Symposium on Ultra-Clean Processing of Semiconductor Devices pp.88-89, (2010).

Google Scholar

[3] S. Suhard, M. Claes, Y. Civale, P. Nolmans, D. Sabuncuoglu Tezcan, Y. Travaly 10th International Symposium on Ultra-Clean Processing of Semiconductor Devices pp.58-59, (2010).

DOI: 10.4028/www.scientific.net/ssp.187.223

Google Scholar

[4] J.R. Burns, C. Ramshaw, R. J Jachuck, Chemical Engineering Science 58 (2003) pp.2245-2253.

Google Scholar

[5] M. Steinert, J Acker, M. Krause, S. Oswald, K,. Wetzig, J. Phys. Chem. B, (2006) pp.11377-11382.

Google Scholar