SiGe Selective Etching to Enable Bottom and Middle Dielectric Isolations for Advanced Gate-All-Around FET Architecture

Hikaru Kawarazaki; Teppei Nakano; Takaaki Ishizu; Takayoshi Tanaka; Wen Liu; Jason Chen; Tomohiko Kawashima; Ai Ping Wu; Farid Sebaai; Ju Geng Lai; Oniki Yusuke; Efrain Altamirano-Sanchez

doi:10.4028/p-MsGv7Q

Paper Titles

Past, Present, and Future of Semiconductor Cleaning Technology
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Nanosheet-Based Transistor Architectures for Advanced CMOS Scaling: Wet Etch and Gas Phase Etch Challenges in Confined Spaces
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On Gas-Phase Selective Dry Etching in 3D Inflections
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SiGe Selective Etching to Enable Bottom and Middle Dielectric Isolations for Advanced Gate-All-Around FET Architecture
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Selectivity Tuning by Peroxide Concentration for the Selective Etching of SiGe20 to Si and SiGe40 to SiGe20
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Investigation of Selective Wet Etching of SiGe Substrates for High-Performance Device Manufacturing
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Highly Selective Etching of SiGe to Si for GAAFET
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Atomic Level Chemical and Structural Properties of Silicon Surface and Initial Stages of Oxidation
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HomeSolid State PhenomenaSolid State Phenomena Vol. 346SiGe Selective Etching to Enable Bottom and Middle...

SiGe Selective Etching to Enable Bottom and Middle Dielectric Isolations for Advanced Gate-All-Around FET Architecture

Abstract:

Formulated chemical ACT^® SG6xxx series demonstrated SiGe etching selective to SiGe with lower Ge concentration. SiGe etching rate on SiGe/Si multi-stack shown steep trend as a function of Ge concentration, resulting in 338 of selectivity between SiGe30% and SiGe15%. Also, apparent loss on SiN and SiO₂ was not observed. Moreover, SiGe etch rate was not impacted by chemical flow in the beaker. It suggests reaction-controlled based etching, which leads to good within wafer uniformity in etching rate of 300mm wafer spin processing. In conclusion, ACT^® SG6xxx series is a promising option for the formation of BDI/MDIs in Nanosheet, Forksheet and CFET.

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Periodical:

Solid State Phenomena (Volume 346)

Pages:

23-28

DOI:

https://doi.org/10.4028/p-MsGv7Q

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Online since:

August 2023

Authors:

Hikaru Kawarazaki*, Teppei Nakano, Takaaki Ishizu, Takayoshi Tanaka, Wen Liu, Jason Chen, Tomohiko Kawashima, Ai Ping Wu, Farid Sebaai, Ju Geng Lai, Oniki Yusuke, Efrain Altamirano-Sanchez

Keywords:

Bottom Dielectric Isolations, Complementary FET, Forksheet, Gate-All-Around (GAA), Middle Dielectric Isolations, Monolithic CFET, Nanosheet, Selective Etching, SiGe

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References

[1] N. Loubet et al., 2017 Symposium on VLSI Technology, p.230

Google Scholar

[2] N. Loubet et al., International Electron Device Meeting (IEDM) 2019, p.11.4.1

Google Scholar

[3] J. Frougier: Solid State Devices and Materials (SSDM) 2021, short course 1.

Google Scholar

[4] N. Horiguchi: 2021 Symposia on VLSI Technology and Circuits, short course 1.

Google Scholar

[5] A. B. Keller, International Electron Device Meeting (IEDM) 2022, p.1

Google Scholar

[6] S. Subramanian et al., 2021 Symposia on VLSI Technology, p.1

Google Scholar

[7] J. Zhang et al., International Electron Device Meeting (IEDM) 2019, p.229

Google Scholar

[8] Y. Oniki: Solid State Devices and Materials (SSDM) 2022, short course 6. 0 2 4 6 8 10 12 14 0 200 400 600 800 1000 1200 SiGe etch rate [nm/min] Magnetic stirrer rotation speed [rpm] SiGe 30% SiGe 15%

Google Scholar