Solid State Phenomena Vol. 346

Abstract: This presentation focuses on semiconductor wafer cleaning technology, one of the most critical technologies in semiconductor device manufacturing for obtaining high yield and reliability, and discusses the past, present, and future of the technology. Emphasis is placed on the review of contamination control and cleaning technologies in the early days since the invention of the transistor. To celebrate the 30+1-year anniversary of the UCPSS, a review will be given of both the first conference held in Leuven in 1992 and the second one held in Bruges in 1994. There will be more research challenges and business opportunities in environmentally benign, innovative damage-free wafer cleaning and surface preparation technologies for future applications.

Abstract: Nanosheet-based transistor architectures for advanced CMOS have sophisticated 3D geometries and aggressively scaled dimensions imposing new challenges to wet etch and gas phase etch. In this paper, we describe three nanosheet-based transistor architectures (nanosheet, forksheet, and CFET) as well as associated challenges for wet etch and gas phase etch at various stages of the process flow, including channel release, work function metal patterning, and controlled dielectric etchback for stacked source-drain formation. The compatibility of etch processes with confined spaces and high-aspect-ratio structures becomes increasingly important for novel nanosheet-based transistor architectures.

Abstract: Semiconductor industry periodically goes through major transitions in the architectures and materials. The previous such transition was the Logic transition to FinFET and NAND transition to 3DNAND that revolutionized the two devices and accelerated PPAC (power, performance, area, cost) progress. Over the last decade, introduction of EUV lithography has driven the device miniaturization and furthered the cause of PPAC, but with the same architecture. The accelerating technological needs at lower cost point with better power efficiency are driving the current push in fundamental architectural changes and new materials introductions, especially in Logic and DRAM with a transition to 3D structures. This moves the critical etches from traditional RIE to selective isotropic etching. Furthermore, newer materials and requirements of better interfaces in these 3D structures are driving the need for dry selective treatments with good isotropicity and free of damage. This paper will give an overview of the current state of selective dry etch and progress in treatments.

Abstract: Formulated chemical ACT^® SG6xxx series demonstrated SiGe etching selective to SiGe with lower Ge concentration. SiGe etching rate on SiGe/Si multi-stack shown steep trend as a function of Ge concentration, resulting in 338 of selectivity between SiGe30% and SiGe15%. Also, apparent loss on SiN and SiO₂ was not observed. Moreover, SiGe etch rate was not impacted by chemical flow in the beaker. It suggests reaction-controlled based etching, which leads to good within wafer uniformity in etching rate of 300mm wafer spin processing. In conclusion, ACT^® SG6xxx series is a promising option for the formation of BDI/MDIs in Nanosheet, Forksheet and CFET.

Abstract: Using two highly efficient inhibitors, one for silicon and one for SiO₂ and SiN it is possible by varying the hydrogenperoxide concentration to achieve tuneable formulated chemistry concerning selectivity. So, the same formulation can be used for the selective etching of SiGe25 vs. Si like for GAA applications as well as for the selective etching of SiGe40 vs. SiGe20 like for CFET applications.

Abstract: The use of SiGe substrate as a semiconductor material is increasing because of its unique properties. In order to manufacture high-performance devices, it is necessary to develop SiGe selective etching technology. In this study, SiGe epi and oxide substrates with varying germanium percentages (15, 25, and 40 %) were used for the investigation of the selective etching process. As the etchant, APM (1:4:20) solutions were used, and added HF and HCl to confirm the pH effect. The evaluation was conducted while adjusting the pH level. In the case of the SiGe epi substrate, the etching rate was very low at high pH, but the etching rate rapidly increased at a specific pH. And then, the etch rate gradually decreased. On the other hand, the etch rates of the oxide substrate rapidly increased as the pH decreased. To explain the etch rate behavior due to the difference in Ge content and type of substrates, the surface chemistry was measured, and the speciation of the solution was analyzed.

Abstract: Highly selective etching of SiGe over Si is required for the fabrication of gate-all-around field-effect transistors (GAAFET). A solution consisting of a mixture of H₂O₂, CH₃COOH, and HF is known to etch SiGe with high selectivity over Si. The detailed etching mechanism of SiGe and Si in this solution was investigated in this study. The effect of each chemical species on the etching of SiGe and Si was investigated using various concentrations of H₂O₂, CH₃COOH, and HF. It was found that the etching rate of SiGe was highly relevant to the concentration of peracetic acid (PAA) which was produced by the reaction between H₂O₂ and CH₃COOH. In addition, various additives which can further increase the SiGe selectivity and their mechanisms were investigated.

Abstract: This work aims to summarize previous results reported in literature on atomic level properties of the wet chemically treated hydrogen-terminated silicon surfaces and of the Si oxidation, in comparison to a model system of ultraclean Si surfaces prepared in ultrahigh vacuum (UHV) conditions. A literature review shows that a proper wet chemical treatment of Si(111) provides an atomically smooth, high-quality surface, similar to the model template obtained in UHV conditions after high temperature heating. However, it seems that Si(111) is an exception among semiconductor surfaces concerning the effects of wet chemistry. Although the insulator films grown by the atomic layer deposition (ALD) have replaced the thermal oxide of SiO₂ in many applications, still an intermediate SiO₂ layer is formed and often grown intentionally beneath the ALD film to improve the device performance. However, a detailed atomic structure of the SiO₂/Si interface is still debatable, which might be due to differences in atomic level smoothness of the used Si(100) starting surfaces.

Abstract: Ultrahigh vacuum (UHV) environment has been widely used in surface science, but UHV technology has been often considered too complex and expensive methodology for large-scale industrial use. Because the preparation of atomically smooth and clean Si surfaces has become relevant to some industrial processes, we have re-addressed the question if UHV could be utilized in these surface tasks using industrially feasible parameters. In particular, we have studied how UHV treatments might be combined with the widely used semiconductor cleaning methodology of wet chemistry.