Papers by Author: Didier Lévy

Abstract: For the 32nm logic technology and beyond, more stringent specifications in terms of dimensions and materials integrity continue to drive the cleaning process improvements. In this paper, post-etch wet cleaning was optimized in order to address CD loss issues and metal hard mask cleaning improvement in a Trench First Hard Mask (TFHM) backend architecture. Based on materials compatibility tests and electrical results, this wet clean process should also be fully compatible with a Via First Trench Last (VFTL) architecture.

Abstract: Integrating multiple gate oxides on a same die requires a proper definition of their respective active area (fig. 1). First the thick gate oxide is grown, and covered by some photoresist. Then a wet etch removes this oxide on the die areas where the resist has been developed. Finally, after resist stripping and surface cleaning, the thin gate oxide is grown. The interaction between the thick oxide surface, the resist and the etchant makes the wet etch challenging. This paper deals with some characterizations and solutions to improve this process.

Abstract: This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.