Papers by Author: Kazuo Arai

Abstract: We investigated the crystalline quality and electrical properties of the channel regions in 4H-SiC buried gate static induction transistors (SiC-BGSITs). To accurately determine the characteristics of the channel regions, we performed transmission electron microscopy and scanning spreading resistance microscopy. It was found that the channel regions have high crystalline quality and no significant fluctuations in doping concentration.

Abstract: Short-circuit capabilities of silicon carbide static induction transistors with the buried gate structures (BGSITs) have been measured for the first time, and have been followed by 2D device simulations. The short-circuit operation of the normally-on type BGSITs is characterized by an abrupt decrease in the output current through a high peak in the initial phase of the short-circuit period, which is distinguished from that of the conventional IGBTs and power MOSFETs. This operation is caused by the inherent operation of the SITs including the non-saturating current-voltage characteristics with the unipolar operation. Decreasing the channel width adequately is a useful method to increase the short-circuit capability.

Abstract: We have fabricated the four pn-type junction TEGs (Test Element Groups) having different structure. Those TEGs are close to the double-implanted (Di) MOSFETs, step by step from the simple pn diode. Voltage-current (V-I) characteristics of the hundred TEGs having p-well structure show similar blocking characteristics of those of simple pn diodes on the same wafer. This indicates that the p-well structure itself does not cause a significant deterioration on the blocking yield. On the other hand, the yield is significantly influenced by the annealing condition for ion-implanted layer. The oxide-related hard breakdown on the JFET region dominates the blocking yield. The reach-through breakdown of the TEGs having the n+ region within each p-well becomes largely suppressed by the high-temperature and short-time annealing.

Abstract: The Ti/4H-SiC Schottky barrier diodes with a field limiting ring (FLR) structure are fabricated. Two types of SBDs are prepared; one (SBD-A) is covered and another (SBD-B) isn’t covered with a carbon cap during high temperature annealing after ion implantation. The breakdown voltage at room temperature for SBD-A and SBD-B are 1400 V and 1000 V, respectively. The breakdown for both SBDs occurs due to an avalanche breakdown. The light emission images are obtained at the breakdown voltage by photo emission microscope (PEM). The light emission is observed along an FLR of the SBD-A as designed. On the other hand, the spot of light emission is observed on a FLR structure of the SBD-B. This light emission spot indicates that leakage current is concentrated because an electrical field concentration is generated at this one for the SBD-B. The root-mean-square roughness of the Al-implanted region on the FLR structure calculated from the atomic force microscopy (AFM) images for the SBD-A and the SBD-B are 0.697 nm and 5.58 nm, respectively. Therefore it is considered that large surface roughness on the FLR decreases breakdown voltage of SBD because an electrical field concentration is generated at a spot.

Abstract: The oxide reliability of metal-oxide-semiconductor (MOS) capacitors on 4H-SiC(000-1) carbon face was investigated. The gate oxide was fabricated by using N2O nitridation. The effective conduction band offset (Ec) of MOS structure fabricated by N2O nitridation was increased to 2.2 eV compared with Ec = 1.7 eV for pyrogenic oxidation sample of. Furthermore, significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. It is suggested that the N2O nitridation as a method of gate oxide fabrication satisfies oxide reliability on 4H-SiC(000-1) carbon face MOSFETs.

Abstract: This paper discusses the issues regarding reliability of large-area (up to 9mm2) gate oxide on the C-face of 4H-SiC. We first show that the initial failure in TDDB characteristics of large area gate oxide is strongly correlated with the surface-defect density. Using wafers with low surface-defect density wafers, scaling analysis of the area-dependence of TDDB characteristics has been performed. It has shown that the reliability of a large area gate oxide is dominated by initial and random failures. Further, we have shown that, by optimizing the temperatures of post-oxidation anneal in hydrogen atmosphere, the random failures of TDDB characteristics are substantially reduced.

Abstract: Reliability of the gate oxide is influenced by the device structure and the processes. In the SiC MOSFET, the surface morphology is degraded by the high temperature activation RTA, and the degradation is remarkable on the n+ source region. This study develops the method to suppress the degradation of the reliability of the gate oxide on the carbon face. By utilizing the carbon cap for the RTA and the high density O2 plasma etching to remove the carbon cap, the reliability is drastically improved both on the un-implanted and the implanted surfaces. Especially, the degradation of the reliability is perfectly suppressed on the un-implanted surface.

Abstract: This paper describes the study of non-hollow-core elementary screw dislocations (SDs) in silicon carbide (SiC) diodes using X-ray microbeam three-dimensional topography. Strain analysis shows that typical screw dislocations having a symmetric strain field tend to cause microplasma breakdown, whereas deformed SDs do not. The symmetry break in SDs will relax the focussing of strain and lessen the formation of defects, thereby leading to the desirable non-leak property.

Abstract: We have carried out detailed investigations on the influence of the growth conditions and the wafer off angle on the surface morphology of low off angle homoepitaxial growth. We found triangular features to be also serious problems on a 4 degree off 4H-SiC Si-face epitaxial layer surface. The control of the C/Si ratio by controlling the SiH4 flow rate is effective in suppressing the triangular features on 4 degree off Si-face homoepitaxial layer. As regards epitaxial growth on a vicinal off-axis substrate, the small off angle difference of a tenth part of a degree has an influence on the surface morphology of the epitaxial layer. This tendency depends on the face polarity and a C-face can be obtained that has a specular surface with a lower vicinal off angle than a Si-face. By controlling this off angle, a specular surface morphology without a bunched step structure could be obtained on a vicinal off angle 4H-SiC Si-face.

Abstract: The turnoff mechanism of SiC buried gate static induction transistors (SiC-BGSITs) were analyzed by three dimensional device simulation. A current crowding occurs in the portion near the channel center away from the gate contact during the initial phase of the turnoff operation, which is resulted from a non-uniform potential distribution through the gate finger with the displacement current flowing there. This increases the turnoff delay time. The impact of source length on the turnoff performance was made clear.