Papers by Author: Yoichiro Tarui

Abstract: Forward voltage of SiC pin diodes is evaluated by device simulation, where a p-type contact is described by Schottky barrier to a p-type surface region. The contact resistance is calculated from the comparison to I-V characteristic of Schottky structure to a p-SiC layer with a sufficiently low Schottky barrier height. Even in the relatively low contact resistance rc of 10-4 Wcm2, non-ohmic current component is observed in Schottky structure to p-SiC and the increase of forward voltage of pin diodes is fairly small. Forward voltage of pin diodes increases in the pin diodes with contact resistance rc over 10-4 Wcm2. The same behavior is also observed irrespective of a time constant of carriers, and doping concentration and thickness of a drift layer.

Abstract: A major crystalline defect which causes a pn junction reverse leakage current has been identified. A faintish stripe defect (FSD), the main cause of the leakage current, was observed in about 90% of the current leak points of our pn diodes. Double shell pits were observed at the edge of the FSD after molten KOH etching, indicating that the FSD is elongated on a basal plane and crosses the epilayer surface. The FSDs are sorted into several groups in terms of the shapes and arrangements of the etch pits. A cross-sectional TEM image of an FSD shows an eight-hold stacked structure, demonstrating that the defect contains a stacking fault. Etch pit observation after repetitive RIE of an epilayer revealed that FSDs originate both in threading dislocations in SiC substrates and from an SiC epitaxial growth process itself.

Abstract: Prototype SiC power modules are fabricated using our class 10 A, 1.2 kV SiC-MOSFETs and SiC-SBDs, and their switching characteristics are evaluated using a double pulse method. Switching waveforms show that both overshoot and tail current, which induce power losses, are suppressed markedly compared with conventional Si-IGBT modules with similar ratings. The total switching loss (MOSFET turn-ON loss, turn-OFF loss and SBD recovery loss) of SiC power modules is measured to be about 30% of that of Si-IGBT modules under the generally-used switching condition (di/dt ~250A/μs). The three losses of SiC modules decrease monotonically with a decrease in gate resistance, namely switching speed. The result shows the potential of unipolar device SiC power modules.

Abstract: 4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer channel which improves the surface where the MOS channel is formed. By the optimization of the epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 m
cm2 is obtained at VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage increase slightly with an increase in temperature. This behavior is favorable for high power operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length and it corresponds to an effective channel mobility of about 20 cm2/Vs.

Abstract: The effect of N2O anneal on channel mobility of inversion-type 4H-SiC n-channel MOSFET has been systematically investigated. It is found that the mobility increases with increasing anneal temperature from 900 to 1150°C. The highest field effect mobility of 30 cm2/Vs is achieved by 1150°C anneal for 3 h, which is about 20 times higher than that for non-annealed MOSFET. In order to investigate the oxide reliability, TDDB measurement has been performed on SiO2 grown on n-type 4H-SiC. The oxide lifetime is found to be drastically improved by N2O anneal.