Package Chip Defect Reduction on Integrated Circuit

Abstract:

This research applies Six Sigma approach in order to reduce defect by increasing the assembly process capability index (Cpk) of Integrated Circuit (IC) production process. This study applies five phases (DMAIC) of Six Sigma approach beginning with define (D), measure (M), analyze (A), improve (I) and control (C) phases, respectively. The response of the research identified in the define phase is the chipped width with Cpk of 0.66 determined from the measure phase. The half-factorial experiments are implemented in the analyze phase to find the significant factors which are water temperature, water pressure and feed rate. In improve phase, the additioanl expriments are performed according to the Box-Behnken design in order to determine the non-linear relation between the chipped width and all mentioned factors. The optimal setting of each factors are determined by applied the response surface optimizer. Under the optimal setting, the control charts are used in the control phase to monitor the chipped width. The resulted Cpk of the response is increased to 1.39 which is greater than the one-sided accpetable process capability of 1.25.

• Periodical: Applied Mechanics and Materials (Volumes 462-463)
• Pages: 578-584
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.462-463.578
• Online since: November 2013
• Authors: Kulpiya Seri, Senjuntichai Angsumalin*
• Keywords: Design of Experiment (DOE), Process Capability, Response Surface Method (RSM), Six Sigma

References

[1] T. Pyzdek, in: The Six Sigma Handbook, McGraw-Hill, USA (2003).

[2] D. Laowattana and N. Vutikorn: Six Sigma Quality Enhancement of Motors through a Vibration Measurement System, KMUTT Research & Development Journal, Vol. 3 (2001), pp.247-267.

[3] P. Boonkliang: Variation Reduction of Acrylic Foam Tape Width in Slitting Process by Six Sigma Approach, Chulalongkorn University Intellectual Repository, (2009).

[4] D. C. Montgomery, in: Introduction to Statistical Quality Control, 6th ed. Wiley, USA (2009).

[5] Z. Jamaluddin, A.M. Razali and Z. Mustafa: Wafer Dice Process Improvement using Six Sigma Approach, 2011 IEEE International Conference on Quality and Reliability (ICQR), Bangkok, Thailand, September 14-17, 2011, pp.31-35.

DOI: 10.1109/icqr.2011.6031676

[6] D. C. Montgomery, in: Design and Analysis of Experiments, 5th ed. Wiley, USA (2001).

[7] W. Rodraksa and W. Tharmmaphornphilas: Appearance Defective Reduction in Nonwoven Process, 2013 International MultiConference of Engineers and Computer Scientists, Hong Kong, March 13-15, 2013, pp.969-974.

[8] P. Ruthaiputpong and N. Rojanarowan: Improvement of Track Zero to Increase Read/Write Area in Hard Disk Drive Assembly Process. Uncertain Supply Chain Management, Vol. 1 (2013), p.165–176.

[9] J. L. Devore, in: Probability and Statistics for Engineering and Sciences, 8th ed. Brooks/Cole, Boston, MA, USA (2011).

[10] A. Senjuntichai: Process Setting through General Linear Model and Response Surface Method. IEANG Transactions on Engineering Technologies, Vol. 5 (2010), pp.237-248.

[11] M. Premngam and A. Senjuntichai: Cycle Time Reduction in Printing and Coloring Process on Front Cover of Camera, 2013 International Conference on Applied Statistics. Maha Sarakham, Thailand, May 14-19, 2013, pp.155-160.

[12] A. Pongtrairat and A. Senjuntichai: Spiral Defect Reduction of Hard Disk Drive Media. Applied Mechanics and Materials. Vol. 421 (2013), pp.93-98.

DOI: 10.4028/www.scientific.net/amm.421.93