Observation of Substrate Silicon Incorporation into Thin Lanthanum Oxide Film during Rapid Thermal Annealing

Abstract:

Lanthanum oxide (La₂O₃) has been proposed as the promising gate dielectric material for future complementary metal-oxide-semiconductor (CMOS) technology. However, unlike the conventional homopolar materials such as silicon oxide or silicon nitride, La₂O₃ is more ionic and in particular at the La₂O₃/Si interface is less thermally stable. This work investigates the chemical and compositional variations of La₂O₃ thin film on the silicon substrate during rapid thermal annealing by using angle-resolved x-ray photoelectron spectroscopy (ARXPS) measurements. Results show that thermal annealing at temperatures above 500 °C would result in the incorporation of substrate Si atoms deep into the bulk of the La₂O₃ film and forming silicate phases both at the interface and in the bulk. These effects would result in the characteristic degradation of CMOS devices.

• Periodical: Advanced Materials Research (Volumes 1120-1121)
• Pages: 414-418
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.1120-1121.414
• Online since: July 2015
• Authors: Jie Qiong Zhang, Dan Qun Yu, Hei Wong, Kuniyuki Kakushima, Hiroshi Iwai
• Keywords: CMOS Technology, High-k, Lanthanum Oxide, Thermal Stability

References

[1] H. Wong, Nano-CMOS Gate Dielectric Engineering, CRC Press, Boca Raton, (2012).

[2] H. Wong and H. Iwai, On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology, Microelectron. Engineer., 138 (2015) 57-76.

DOI: 10.1016/j.mee.2015.02.023

[3] H. Yamada, T, Shimizu, A. Kurokawa, K. Ishii, and E. Suzuki, MOCVD of high-dielectric-constant lanthanum oxide thin films, J. Electrochem. Soc. 150 (2003) G429-G435.

DOI: 10.1149/1.1585055

[4] K. Kakushima, K. Tachi, P. Ahmet, K. Tsutsui, N. Sygii, and T. Hattori, Advantage of further scaling in gate dielectric below 0. 5 nm of equivalent oxide thickness with La2O3 gate dielectrics, Microelectron. Reliab., 50 (2010) 790-793.

DOI: 10.1016/j.microrel.2010.02.001

[5] D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, M. P. Agustin, Y. Yang, S. Stemmer, L. V. Goncharova, T. Gustafsson, and  E. Garfunkel, Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction, J. Appl. Phys., 98, (2005).

DOI: 10.1063/1.1988967

[6] H. Yamada, T. Shimizu and E. Suzuki, Interface reaction of a silicon substrate and lanthanum oxide films deposited by metalorganic chemical vapor deposition, Jpn. J. App. Phys., 41 (2002) L368-370.

DOI: 10.1143/jjap.41.l368

[7] H. Wong, H. Iwai, K. Kakushima, B. L. Yang, and P. K. Chu, XPS study of the bonding properties of lanthanum oxide/silicon interface with a trace amount of nitrogen incorporation, J. Electrochemical Soc., 157 (2010) G49-G52.

DOI: 10.1149/1.3268128

[8] Database of electron inelastic mean free path for elemental solids. Available at: http: /www. nims. go. jp/research/organization/hdfqf1000000isjt-att/hdfqf1000000ispa. pdf.

[9] S. Inamoto, J. Yamasaki, E. Okunishi, K. Kakushima, H. Iwai, and N. Tanaka, Annealing effects on a high-k lanthanum oxide film on Si (001) analyzed by aberration-corrected transmission electron microscopy/scanning transmission electron microscopy and electron energy loss spectroscopy, J. Appl. Phys., 107 (2010).

DOI: 10.1063/1.3445874

[10] H. Nohira, A. Komatsu, K. Yamashita, K. Kakushima, H. Iwai, Y. Hoshi, and Y. Shiraki, XPS study on chemical bonding states of high-κ/high-μ gate stacks for advanced CMOS, J. Electrochemical Soc., 41 (2011) 137-146.

DOI: 10.1149/1.3633293