We present a concept for integration of low temperature fabricated memory devices in a 3-D architecture using a hybrid silicon-organic technology. The realization of electrically erasable read-only memory (EEPROM) like device is based on the fabrication of a V-groove SiGe MOSFET, the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir-Blodgett (LB) technique. Such structures were processed at a temperature lower than 400°C following a process based on wafer bonding. The electrical characteristics of the final hybrid MISFET memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented.